AMD EPYC 8005 Launch: Up to 84 Zen 5 Cores in a 225 W Package

Technical announcement

AMD officially lifted the embargo on the EPYC 8005 “Sorano” series at the Mobile World Congress 2026. The new family is the first EPYC line to abandon the low‑power Zen 4c core design in favor of full‑blown Zen 5 cores across the entire product stack. This architectural shift brings a substantial increase in per‑core performance, L3 cache capacity and memory bandwidth, while still targeting the 200 W‑225 W power envelope that data‑center operators have come to expect from the SP6‑compatible platform.

Specifications

SKU	Zen 5 cores	Threads	Base clock	L3 cache	Default TDP	List price (1 KU)
EPYC 8635P	84	168	1.6 GHz	384 MiB	225 W	$5,799
EPYC 8535P	64	128	2.0 GHz	256 MiB	210 W	$5,499
EPYC 8435P	48	96	2.45 GHz	256 MiB	200 W	$4,999
EPYC 8325P	32	64	2.7 GHz	256 MiB	175 W	$4,299
EPYC 8225P	24	48	2.95 GHz	128 MiB	160 W	$3,799
EPYC 8125P	16	32	2.65 GHz	128 MiB	125 W	$799
EPYC 8025P	8	16	2.9 GHz	64 MiB	95 W	$529

Key technical changes compared with the prior EPYC 8004 “Siena” line:

• Core architecture: Full Zen 5 cores replace Zen 4c, increasing per‑core IPC by ~15 % and adding 2 MiB of L3 per core.
• Clock speeds: Boost frequencies now reach 4.5 GHz on turbo, versus a 3.15 GHz ceiling on Siena.
• Memory: Native support for DDR5‑6400, double the bandwidth of DDR4‑3200 platforms.
• PCIe: 96 lanes of PCIe 5.0 per socket, matching the EPYC 9005 family.
• Power envelope: Maximum TDP raised to 225 W to accommodate the higher core count while keeping the SP6 platform’s 1U/2U thermal design intact.

Real‑world implications

Server density and workload fit

The 84‑core EPYC 8635P is aimed at dense cloud workloads—high‑throughput web serving, in‑memory databases, and large‑scale virtualization. Its 384 MiB L3 cache reduces memory latency for cache‑heavy applications, while the 225 W TDP still fits within most 2U chassis equipped with high‑efficiency cooling. For edge and telco deployments where power is at a premium, the 16‑core EPYC 8125P and 8‑core EPYC 8025P provide a sweet spot: more cores than the legacy EPYC 4005, but with a modest 125 W/95 W draw and DDR5‑6400 bandwidth that can accelerate packet processing and storage stacks.

Platform compatibility

All Sorano SKUs are validated on the SP6 platform, which includes 8‑channel DDR5 memory and up to 12 × NVMe slots. Motherboard vendors such as ASRock Rack and Supermicro have already published BIOS updates for the 2U12L2S and AS‑1115SV WTNRT models, respectively, enabling the new CPUs without a hardware redesign. The only notable change for integrators is the need for a 225 W power supply rail on the highest‑core‑count boards; most 2U SP6 systems already provision 250 W per socket, so the impact is minimal.

Competitive positioning

Against Intel’s Xeon 6 SoC family, the EPYC 8005 series offers:

• Higher core density (up to 84 vs. 56 cores on Xeon 6)
• More PCIe lanes (96 vs. 80 per socket)
• Lower idle power for comparable core counts (thanks to Zen 5’s efficiency) The trade‑off is the absence of integrated Ethernet NICs and vRAN boost accelerators that Intel bundles on the Xeon 6 SoC. Operators that rely on separate SmartNICs or external DPDK‑accelerated cards will find the EPYC 8005’s PCIe headroom advantageous, while those seeking a single‑chip solution may still favor Intel for specific telco workloads.

Deployment considerations

1. Thermal design – Verify that the chassis can sustain 225 W per socket under sustained load; the SP6 reference design uses a 300 mm heatsink with dual 140 mm fans, which is adequate for 84‑core chips at typical utilization.
2. Memory planning – DDR5‑6400 modules are now the baseline; plan for 8‑channel configurations to hit the full 102.4 GB/s per socket bandwidth.
3. Power budgeting – While the 225 W TDP is higher than Siena’s 200 W, the overall system power draw remains comparable because the newer cores achieve higher performance per watt.
4. Software stack – Ensure that the operating system kernel and hypervisor are updated to recognize the new Zen 5 core topology (e.g., Linux 6.9+ with the zen5 scheduler patches).

Outlook

The EPYC 8005 “Sorano” line expands AMD’s tiered offering, filling the gap between the low‑core‑count EPYC 4005 and the ultra‑dense EPYC 9005 “Turin Dense”. Early adopters in edge, telco and high‑performance storage can expect a noticeable uplift in throughput without a proportional increase in power or cooling costs. Follow‑up benchmarks from ServeTheHome will detail real‑world performance on VMs, container workloads and NVMe‑over‑Fabric stacks.

Stay tuned for in‑depth latency and throughput measurements as the chips hit the bench.