Recreating the Apollo Guidance Computer in Modern Silicon: A Technical Deep Dive into the `apollo11_fpga` Project

The Apollo Guidance Computer represents one of the most remarkable achievements in the history of computing. Weighing just 70 pounds and consuming only 70 watts of power, this 16-bit machine guided astronauts to the lunar surface and back with a mere 72 kilobytes of memory and a clock speed measured in kilohertz. Today, decades later, the AGC's architecture continues to fascinate engineers and historians alike. Mike Kohn's apollo11_fpga project offers a compelling technical exploration of this historic system, implementing the core CPU functionality on a modern Lattice iCE40 HX8K FPGA running at 6 MHz—a speed that would have been considered impossibly fast to the original designers.

Architectural Fidelity and Modern Compromises

The project's README reveals a thoughtful approach to historical reconstruction. Kohn explicitly states this is "mostly just the CPU portion," with peripherals either omitted or replaced with similar concepts. This pragmatic decision reflects a common challenge in hardware preservation: the original AGC's I/O system was deeply integrated with specific spacecraft hardware—gyroscopes, accelerometers, optical systems, and communication links that have no direct modern equivalent. Rather than attempting to emulate every transistor and wire, the implementation focuses on the computational core, the essential logic that made the AGC's unique architecture function.

One significant architectural deviation involves memory organization. The original AGC used 16-bit memory words where the upper 15 bits stored data and the lowest bit served as a parity bit—a critical reliability feature for spaceflight. Kohn's implementation inverts this: the lower 15 bits contain data, with the upper bit typically clear. This change simplifies the FPGA implementation while maintaining functional equivalence for software that doesn't rely on parity checking. Similarly, instruction timings differ from the original specifications. The original AGC's instruction cycle times were meticulously documented (with measurements like 11.7 microseconds for a single MCT—Memory Cycle Time), but Kohn notes these timing constraints weren't implemented since the project "will probably never run the original software, nor will it land on the moon." This represents a philosophical choice: the implementation prioritizes functional correctness over temporal accuracy, focusing on the computational model rather than the exact temporal behavior.

The AGC's Unique Instruction Set Architecture

The AGC's instruction set reveals fascinating design decisions shaped by the constraints of 1960s technology. Unlike modern processors with extensive instruction sets, the AGC used a compact 15-bit instruction format, with opcodes encoded in just a few bits. Kohn's implementation includes the complete instruction set, from basic arithmetic operations like ca (Clear and Add) and cs (Clear and Subtract) to more complex operations like das (Double Add to Storage) and mp (Multiply).

What makes the AGC's architecture particularly interesting is its 1's complement arithmetic system. Unlike modern computers that use two's complement for signed integers, the AGC represented negative numbers using 1's complement. In this system, positive zero (0_00_0000_0000_0000) and negative zero (1_00_0000_0000_0000) are distinct values—a concept that can trip up modern programmers. The implementation details show how fractions were represented: 1/2 becomes 0_10_0000_0000_0000, where bit 14 serves as the sign bit, and bits 13-0 represent the fractional value scaled by 2^14. This fixed-point arithmetic system allowed the AGC to perform complex navigation calculations without floating-point hardware.

The project also implements the AGC's double-precision mode, where the A and L registers combine into a 29-bit register. The sign bit (bit 28) comes from register A, followed by 14 bits from A's lower portion, and finally 14 bits from L's lower portion. This clever register pairing enabled more precise calculations while working within the 15-bit word size constraint.

Memory Architecture: Banks and Overlaps

The AGC's memory system was remarkably sophisticated for its era. The original system featured 8 banks of erasable memory (RAM), each 256 words, totaling 2048 words of volatile storage. Kohn's implementation maps this to the FPGA's block RAM, maintaining the banking structure that allowed the AGC to expand its addressable memory beyond the 15-bit address space limitation.

More complex is the fixed memory (ROM) architecture. The AGC used 36 banks of 1024 words each, with 32 banks selected via the FB (Fixed Bank) register and 5 additional banks accessed through a super bank bit in I/O channel 7. The implementation maps this to 16-bit memory across 4096 addresses, a pragmatic simplification that preserves the banking concept while adapting to the FPGA's memory organization.

The memory map reveals the AGC's hybrid nature: it combined erasable memory for variables and temporary storage with fixed memory for program code and constants. The overlapping memory regions (where different banks share physical addresses depending on configuration) demonstrate the careful resource optimization required in 1960s computing—every bit of memory was precious.

Peripheral Emulation and Modern Adaptations

While the original AGC interfaced with spacecraft systems like the Inertial Measurement Unit (IMU), optical systems, and communication links, Kohn's implementation provides modern alternatives. The I/O system includes:

• Display interface: A 4x7-segment display controller and display busy flag
• SPI communication: For LCD or other peripheral communication
• Input devices: A joystick interface with fire button and four axis inputs
• LED indicators: Simple binary output for debugging

These adaptations serve a dual purpose: they provide functional equivalents for testing and demonstration, while also serving as educational tools. A student can interact with the AGC implementation through a joystick and display, gaining intuition about how astronauts might have interacted with the original DSKY (Display and Keyboard) interface.

The interrupt system is particularly well-documented. The AGC supported multiple interrupt vectors for time-based events (T3RUPT, T4RUPT, T5RUPT, T6RUPT) and external events. Kohn's implementation preserves the interrupt handling mechanism, including the automatic saving of registers and the precise rules about when interrupts could occur (not during multi-word instruction processing or skip instructions). This attention to detail ensures that the temporal behavior of interrupt-driven code remains predictable, even if the exact timing differs from the original.

Technical Implementation on FPGA

The choice of the Lattice iCE40 HX8K FPGA is significant. This chip provides 8,280 logic cells, 128 kilobytes of block RAM, and sufficient I/O for the implementation. Running at 6 MHz, the FPGA executes the AGC instructions at a speed that would have been unimaginable in the 1960s—approximately 500 times faster than the original AGC's 2 MHz clock (though the AGC's effective instruction rate was much lower due to its complex microcode).

The implementation likely uses the FPGA's block RAM for the AGC's memory, with the CPU logic synthesized from Verilog or VHDL code. The 15-bit word size presents an interesting challenge: modern FPGAs are optimized for 8, 16, 32, or 64-bit operations. Implementing 15-bit arithmetic requires careful handling of overflow and sign extension, particularly for the 1's complement system where negative zero exists.

Kohn's project references several key sources for the AGC specifications:

• The Apollo Guidance Computer Assembly Language Manual for instruction details
• Ken Shirriff's analysis of the AGC's divide instruction
• The original Apollo Guidance, Navigation, and Control manual for comprehensive system documentation

These references demonstrate the project's grounding in historical research rather than mere speculation.

Educational and Historical Value

The apollo11_fpga project serves multiple purposes beyond technical curiosity. For hardware engineers, it provides a concrete example of implementing a non-standard architecture on modern FPGAs—a valuable exercise in digital design. For computer scientists, it offers insight into alternative instruction set design, fixed-point arithmetic, and resource-constrained computing.

More profoundly, the project connects modern practitioners to a pivotal moment in computing history. The AGC's development coincided with the birth of integrated circuit technology and the early days of software engineering. Its architecture reflects the constraints and creative solutions of that era: the 15-bit word size, the 1's complement arithmetic, the bank-switched memory, and the interrupt-driven real-time system. By implementing this architecture in modern silicon, Kohn preserves not just the computational model but the design philosophy—elegant solutions to severe constraints.

Limitations and Future Directions

The project acknowledges its limitations. It doesn't implement the exact instruction timings, doesn't run the original Apollo software, and omits many peripherals. These are reasonable compromises for an educational project, but they also highlight the gap between historical reconstruction and functional emulation.

Future enhancements could include:

• Timing accuracy: Implementing cycle-accurate instruction timing for historical fidelity
• Original software: Porting or adapting Apollo flight software to run on the FPGA implementation
• Peripheral expansion: Adding more spacecraft-specific interfaces like the IMU or communication systems
• Verification: Creating test suites that validate the implementation against known AGC behavior

Conclusion

Mike Kohn's apollo11_fpga project represents a thoughtful intersection of historical preservation and modern digital design. By implementing the Apollo Guidance Computer's core architecture on contemporary FPGA hardware, the project makes this historic system accessible for experimentation and study. The implementation choices—focusing on the CPU core, adapting the memory system, and providing modern peripheral alternatives—reflect a pragmatic approach to historical reconstruction.

For engineers and historians alike, the project offers a tangible connection to one of computing's most remarkable achievements. It demonstrates how the constraints of 1960s spaceflight drove innovative solutions that remain relevant today: efficient use of limited resources, robust error handling, and real-time responsiveness. While the AGC will never again guide spacecraft to the moon, its architectural lessons continue to inform modern embedded systems design.

The project invites us to consider not just how the AGC worked, but why it was designed that way—and what we might learn from its approach to solving problems under extreme constraints. In an era of abundant computing resources, the AGC's elegant minimalism serves as a reminder that sometimes, less truly is more.

For those interested in exploring the project further, visit the GitHub repository and the project documentation page for additional technical details and implementation notes.