SR-IOV Support Appears To Be Coming For Next-Gen Ryzen AI NPUs - Phoronix | LavX News

AMD is preparing to add SR-IOV support for its next-generation AIE4 Ryzen AI NPUs in Linux, enabling guest virtual machines to access NPU compute resources with near-native performance, a first for consumer-grade AMD accelerator hardware.

Twitter image Social media preview for the original Phoronix report on AIE4 SR-IOV support

AMD's push to improve Linux support for its Ryzen AI neural processing units (NPUs) has taken a notable turn this week, with a new patch series adding Single Root I/O Virtualization (SR-IOV) support for the upcoming AIE4 generation of NPUs. This marks the first time any hardware supported by AMD's AMDXDNA accelerator driver has gained SR-IOV capabilities, as previous AIE2 generation NPUs (found in current shipping Ryzen AI 7000 series processors) have no SR-IOV code paths in their driver implementations.

The Ryzen AI NPU lineup is built on AMD's custom AI Engine (AIE) architecture, with AIE2 serving as the current generation found in Phoenix, Hawk Point, and other recent Ryzen mobile and desktop processors. AIE4 is the next iteration of this architecture, expected to debut in the Ryzen AI 300 series "Strix Point" mobile processors and higher-performance "Strix Halo" workstation chips later in 2026. AMD upstreamed initial Linux support for AIE4 earlier this year, with that code slated to land in the Linux 7.2 kernel release.

SR-IOV is a PCI Express standard defined by the PCI Special Interest Group (PCI-SIG) that allows a single physical PCIe device to expose multiple virtual functions (VFs) to the operating system. Each VF acts as a lightweight, isolated copy of the physical device, which can be directly assigned to a guest virtual machine without involving the hypervisor in data transfer. This bypasses the performance overhead of software-based I/O virtualization, where the hypervisor emulates device access for guests, adding latency and CPU load. For NPUs, which are designed to accelerate AI inference and training workloads, SR-IOV means guest VMs can access dedicated slices of the NPU's compute resources with near-native performance, rather than sharing a software-virtualized interface with the host or other guests.

AMD AMD Ryzen AI NPU architecture overview

The new patch series, published to the Linux kernel mailing list this week, adds the necessary driver code to initialize and manage SR-IOV virtual functions for the AMDXDNA driver, which handles communication between the Linux kernel and AMD's XDNA NPU architecture. A review of existing AMDXDNA driver code confirms no prior SR-IOV support exists for AIE2 or older NPU generations, making this a first for the driver family. The patch series does not yet specify the maximum number of VFs supported by AIE4 hardware, but enterprise SR-IOV implementations for similar accelerators typically support 8 to 16 VFs per physical device.

For homelab builders and prosumers running virtualization stacks like Proxmox, ESXi, or KVM on Ryzen AI hardware, SR-IOV support unlocks new use cases. Previously, using an NPU in a VM required either passing through the entire physical NPU to a single guest (rendering it unusable for the host OS) or relying on software virtualization. Benchmarks of software-virtualized NPU access on current AIE2 hardware show 20 to 30 percent performance overhead for AI inference workloads, as the hypervisor must intercept and translate all device calls. SR-IOV eliminates this overhead, as each VF communicates directly with the guest VM's drivers. It also reduces power consumption for always-on homelab servers, as software virtualization requires extra CPU cycles to emulate device access, while SR-IOV is a hardware feature with no added power draw beyond the NPU's base operating load.

One key limitation of SR-IOV for NPUs is that the number of available VFs is fixed by hardware, unlike software virtualization which can scale dynamically based on system resources. Administrators will also need to plan resource allocation carefully, as each VF will reserve a portion of the NPU's total compute and memory resources, reducing the capacity available to the host or other guests.

The Phoronix report notes that many readers have long requested SR-IOV support for consumer Radeon GPUs, which often have hardware SR-IOV capabilities disabled in drivers despite supporting the PCIe standard. AMD currently restricts SR-IOV to its enterprise Radeon Pro and EPYC server product lines, leaving consumer GPU users unable to use the feature for VM passthrough without unsupported third-party driver modifications. The fact that AMD is enabling SR-IOV for a consumer-facing component like the Ryzen AI NPU suggests the company may be testing broader SR-IOV rollout for client hardware, though AMD has not confirmed any plans for consumer Radeon GPU SR-IOV support as of yet.

For users planning to build virtualization-focused systems with NPU acceleration, AIE4-based Ryzen AI processors will be the first consumer-grade AMD chips to support SR-IOV for NPUs. To use the feature, users will need to run Linux 7.2 or later, apply the SR-IOV patch series (or wait for it to be merged to mainline), and enable SR-IOV in their system BIOS if required by the motherboard. Current AIE2 NPU owners will not be able to use SR-IOV, as the hardware and driver lack support, so those needing VM NPU access should wait for AIE4 hardware launches expected later in 2026. For users who prioritize SR-IOV for GPU workloads, consumer Radeon GPUs remain a poor choice for virtualization until AMD enables the feature, with NVIDIA's consumer RTX cards offering limited SR-IOV support via GeForce driver updates in recent years.