Overview
Pipelining increases instruction throughput by breaking down the execution of an instruction into several stages (e.g., Fetch, Decode, Execute, Write-back). While one instruction is being executed, the next one is being decoded, and the one after that is being fetched.
Stages
- Instruction Fetch (IF): Retrieve the instruction from memory.
- Instruction Decode (ID): Determine what the instruction does.
- Execute (EX): Perform the operation.
- Memory Access (MEM): Read or write data if necessary.
- Write-back (WB): Store the result in a register.
Hazards
- Structural Hazards: Resource conflicts (e.g., two stages needing the same bus).
- Data Hazards: An instruction depends on the result of a previous instruction still in the pipeline.
- Control Hazards: Caused by branches that change the flow of execution.