AMD's Enterprise CPU and GPU roadmap: Venice, Verano, Zen 6, Helios, and CDNA

AMD has unveiled an ambitious data center roadmap spanning 2026 and 2027, marking a significant shift in the company's strategy as it transitions from underdog to major player in the server market. With enterprise CPU market share climbing from less than 1% in 2017 to nearly 29% by late 2025, AMD is now positioning itself to challenge Nvidia's dominance in AI and high-performance computing through a comprehensive portfolio of processors, accelerators, and rack-scale systems.

2026 CPUs: Venice and Venice-X — featuring up to 256 Zen 6 cores

The centerpiece of AMD's 2026 lineup is the EPYC Venice processor, built on the company's next-generation Zen 6 microarchitecture and manufactured on TSMC's cutting-edge N2 (2nm-class) process technology. This represents AMD's first data center design to leverage 2nm fabrication, enabling substantial performance and efficiency gains.

Venice will scale up to 256 high-performance Zen 6 cores, representing a 33% increase over the current EPYC Turin processors that top out at 192 Zen 5c cores. The processor will adopt an all-new SP7 form factor designed to accommodate more compute complex dies (CCDs) on the package, increase memory channels, enhance I/O capabilities, and boost peak power delivery to feed the additional cores.

Memory bandwidth receives a dramatic upgrade, with Venice providing up to 1.6 TB/s of per-socket memory throughput—more than doubling the 614 GB/s available on current EPYC CPUs. AMD is likely to support advanced memory modules such as MR-DIMM or MCR-DIMM to achieve this bandwidth increase, addressing the growing memory demands of AI and HPC workloads.

Connectivity with accelerators sees similar improvements, with AMD planning to double CPU-to-GPU bandwidth by adopting PCIe 6.0. This standard can deliver roughly 128 GB/s of bidirectional bandwidth per link before encoding overhead. With up to 128 PCIe lanes, Venice should be capable of moving substantially larger volumes of data between CPUs and accelerators.

AMD claims the EPYC Venice processor will deliver up to 70% higher performance compared with the existing EPYC 9005-series, though the company has not specified the workloads used for this comparison. The roadmap also teases EPYC Venice-X with extra L3 cache as part of sovereign AI and HPC platforms featuring the Instinct MI430X and MI440X accelerators, though details remain scarce.

2027 CPUs: Verano — A brand-new design, or Zen 6 with BSPDN?

AMD's EPYC Verano high-performance processors, planned for 2027, represent the company's next evolution in data center computing. While AMD has not officially confirmed whether Verano represents a seventh-generation EPYC offering or a Zen 6+ variant, the timing aligns with TSMC's A16 fabrication process ramp, expected to enter high-volume production in late 2026.

A16 will be TSMC's first manufacturing node to incorporate backside power delivery, a feature designed to improve power distribution and efficiency for large datacenter CPUs and AI accelerators. This technology could provide AMD with a "free" performance upgrade while gaining valuable experience building processors with a backside power delivery network (BSPDN) without moving to an all-new microarchitecture.

Verano processors are specifically designed to power AMD's next-generation rack-scale AI system, though specific core counts and architectural details remain undisclosed. The processors will likely feature tangible enhancements over Venice, potentially including improved power efficiency and higher clock speeds enabled by the A16 process technology.

2026 AI Accelerators: Instinct MI400 series — different subsets of CDNA 5

AMD's Instinct MI400-series data center GPUs represent a strategic shift toward workload-specific accelerator designs. The company will offer three distinct products based on different subsets of the CDNA 5 architecture, each aimed at different types of workloads and deployments.

The Instinct MI440X and MI455X models are designed primarily for low-precision AI computation, supporting data formats such as FP4, FP8, and BF16. The MI440X will serve as the foundation of AMD's Enterprise AI platform, which uses AI servers based on one EPYC Venice CPU and eight Instinct MI440X accelerators. These machines are designed for on-premises AI deployments for training and inference, featuring power consumption and cooling requirements compatible with existing data center infrastructure.

The Instinct MI455X represents AMD's flagship AI offering, designed to deliver maximum performance when installed into AMD's Helios rack-scale systems, which will be liquid-cooled. AMD projected the MI455X to offer 2X performance increase, 50% more memory capacity, and over 100% bandwidth growth compared to the Instinct MI355X. The accelerator is set to hit 40 dense FP4 PFLOPS, slightly lower than Nvidia's Rubin GPU, which is expected to offer 50 dense FP4 PFLOPS.

By contrast, the Instinct MI430X targets sovereign AI and HPC environments, supporting both FP32 and FP64 precision required for traditional technical computing and supercomputing workloads. AMD envisions customers deploying MI430X accelerators will also use EPYC Venice-X processors that add extra cache and offer enhanced single-thread performance.

All three MI400-series accelerators will use Infinity Fabric for intra-package connectivity, while AMD plans to deploy UALink for scale-up connectivity. This industry-standard interconnection for AI accelerators depends on ecosystem support from companies such as Astera Labs, Auradine, Enfabrica, and Xconn. Recent rumors suggest AMD is exploring UALink-over-Ethernet connectivity options.

2026 / 2027 rack scale platform: Helios — AMD's first rack-scale AI system

Helios represents AMD's first rack-scale AI system, combining EPYC Venice CPUs with 72 Instinct MI455X accelerators interconnected using UALink or UALink-over-Ethernet. The system offers 31 TB of HBM4 memory with 1400 TB/s of bandwidth and delivers 2900 FP4 dense PFLOPS of compute performance.

The Helios platform will use Pensando Vulcano network interface cards (NICs), expected to be among the industry's first 800 GbE network cards compliant with the Ultra Ethernet specification. While Helios will be behind Nvidia's VR200 NVL72 system in terms of compute performance, its greater HBM4 memory capacity may provide an edge in memory-dependent workloads.

Recent rumors indicated potential delays in widespread availability of Instinct MI455X accelerators and Helios rack-scale systems from the second half of 2026 to Q2 2027—reports AMD quickly denied. However, uncertainties surrounding UALink switch availability in calendar 2026 impact sentiment about AMD's rack-scale solutions relying on this industry-standard interconnection.

Given AMD's multi-billion-dollar deals with AI companies to supply future AI systems, the first batches of rack-scale MI455X UALoE72 systems may be exclusively available to companies like Meta and OpenAI, with broader availability expected in 2027.

2027 AI Accelerators: Instinct MI500 series — CDNA 6 and 256-way MegaPod

Looking further ahead, AMD is developing the Instinct MI500-series accelerators based on the CDNA 6 architecture. The next-generation AI rack, tentatively called Instinct MI500 UAL256, spans three interconnected racks and represents AMD's most ambitious AI solution to date.

The system architecture packs 64 EPYC Verano CPUs and 256 Instinct MI500-series GPU packages. Two outer racks each contain 32 compute trays integrating one EPYC Verano processor and four Instinct MI500 accelerators, while the central rack hosts 18 trays dedicated to UALink switches that link the cluster together. In total, the deployment includes 64 compute trays and 256 GPU modules.

Given the power density of modern AI accelerators, the MI500 MegaPod will rely on liquid cooling for both compute trays and networking hardware. Compared to Nvidia's Kyber VR300 NVL576 pod, which integrates 144 quad-chiplet GPUs, AMD's MI500 UAL256 configuration provides about 78% more GPU packages per system.

However, it remains unclear whether the platform can match the expected performance of NVL576, projected to deliver 147 TB of HBM4 memory and roughly 14,400 FP4 PFLOPS of compute. AMD is expected to introduce the system in late 2027, roughly when Nvidia's VR300 NVL576 Kyber platforms are anticipated to arrive.

If this timeline holds, both companies will likely ramp production of their respective MI500-series and Rubin Ultra-based rack-scale systems in 2028. With increasing amounts of AMD's revenues stemming from data center workloads, the company must remain competitive beyond 2027 to challenge future architectures like Nvidia's Feynman architecture.

AMD's comprehensive roadmap demonstrates the company's commitment to becoming a full-stack provider of data center solutions, from CPUs and GPUs to complete rack-scale systems. By aligning product releases with manufacturing process advancements and industry-standard interconnects, AMD is positioning itself to capture significant market share in the rapidly evolving AI and HPC segments while maintaining its momentum in traditional enterprise computing.