AMD showcased its next-gen server hardware including 256-core Venice CPUs, MI455X GPUs with 320B transistors, and the 2.9 EFLOPS Helios rack system during CES 2026 keynote demonstrations.

At CES 2026, AMD displayed its forthcoming data center components including Venice EPYC processors, Instinct MI455X accelerators, and the Helios rack-scale system. These products represent AMD's 2026 server roadmap with architectural advancements in packaging and density.
Venice EPYC: 256 Zen 6 Cores via 2.5D Packaging

Venice marks AMD's first server CPU using 2.5D packaging, featuring dual I/O dies surrounded by eight Zen 6 CCDs. This configuration enables 256 cores per socket, manufactured on TSMC's 2nm process. The physical layout confirms AMD's shift from monolithic designs, though exact interconnect details remain undisclosed. Performance projections indicate significant throughput gains over current Turin processors, particularly in highly threaded workloads.
Key Venice specifications:
- Core count: 256
- Manufacturing process: TSMC 2nm
- Package type: 2.5D with central I/O dies
- Expected launch: Q4 2026
Instinct MI455X: 320B-Transistor AI Accelerator

The MI455X GPU features twelve chiplets fabricated on mixed 2nm/3nm nodes, surrounded by twelve 36GB HBM4 stacks. With 320 billion transistors, it targets rack-scale AI deployments. AMD confirmed three MI400-series variants:
| Model | Use Case | Configuration |
|---|---|---|
| MI455X | AI Training | Rack-scale |
| MI440X | 8-way Servers | Power-optimized |
| MI430X | HPC | High FP64 performance |
The MI500 series roadmap (CDNA 6 on 2nm with HBM4e) was confirmed for 2027 release.
Helios Rack-Scale Deployment
AMD's 7000-pound Helios system integrates both Venice CPUs and MI455X GPUs in a double-width rack. Each compute tray contains four MI455X accelerators and one Venice processor, scaling to 72 GPUs and 18 CPUs per rack. Total FP4 AI performance reaches 2.9 EFLOPS with Pensando networking handling scale-out requirements.
System builders targeting AI infrastructure should evaluate Helios for large clusters, while traditional data centers may consider MI440X configurations for 8-way GPU nodes. Power efficiency metrics remain undisclosed pending final silicon validation.

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