ARM Targets 128‑Bit Page Tables in Linux Kernel with FEAT_D128

Announcement

On 13 May 2026, ARM announced that the next revision of its architecture, Armv9.3, will include an optional feature called FEAT_D128. The feature adds support for 128‑bit page‑table entries (PTEs) in the VMSAv9‑128 translation regime. A patch series marked RFC has been submitted to the mainline Linux kernel, allowing developers to experiment with the new translation format before it becomes mandatory in silicon.

Technical specifications

Aspect	Current implementation	With FEAT_D128
PTE width	64 bits	128 bits
Physical address space	48 bits (256 TiB)	64 bits (16 EiB)
Virtual address space	48 bits (256 TiB)	64 bits (16 EiB)
Reserved bits for extensions	~12 bits per entry	~76 bits per entry

How the 128‑bit format works

The VMSAv9‑128 translation system keeps the existing four‑level page‑table walk but doubles the size of each descriptor. The extra 64 bits sit after the traditional fields (valid, type, access permissions, etc.) and are interpreted by the MMU as follows:

1. Physical address high half – enables addressing beyond the 48‑bit limit used today.
2. Extended attribute bits – reserved for future hardware features such as cache‑policy extensions, protection‑key granularity, and per‑page telemetry.
3. Software‑defined flags – allow the kernel to store per‑page metadata without needing separate data structures.

The extension is optional; silicon can expose the feature via the ID_AA64MMFR3_EL1 register. Linux will check this register during early boot and enable the VMSAv9‑128 path only when the CPU reports FEAT_D128 support.

Kernel integration status

• A request‑for‑comments (RFC) patch set landed in the arm64 tree in early May 2026. The series adds:
  • New CONFIG_ARM64_FEAT_D128 Kconfig option.
  • arch/arm64/mm/ changes to allocate 128‑bit PTEs and to translate them during page‑walk.
  • Early‑boot detection logic that falls back to the classic 64‑bit format if the feature is absent.
• Known gaps – KVM hypervisor, Kernel Address Sanitizer (KASAN), and some debugging facilities still rely on the 64‑bit layout. Patches for these subsystems are being tracked in separate branches.
• The RFC is open for community testing; developers are encouraged to run the patches on ARM development boards that already expose the feature via an FPGA‑based prototype.

Market implications

Server‑grade ARM silicon

Major cloud providers have been scaling ARM‑based instances to 256 GiB of RAM per socket. With 128‑bit PTEs, a single socket could theoretically address up to 16 EiB of physical memory, removing a hard ceiling that forces multi‑socket designs for ultra‑large in‑memory databases. Chip designers such as Ampere, Marvell, and NVIDIA are likely to adopt FEAT_D128 in their next‑generation cores to differentiate their offerings for high‑performance computing (HPC) and AI workloads.

Impact on virtualization

KVM’s current page‑table handling assumes 64‑bit entries. The lack of immediate support means that early adopters will need to run VMs in a compatibility mode, limiting the benefit of larger address spaces. However, once KVM is updated, hypervisors could allocate multiple terabytes of guest RAM without resorting to nested paging tricks, simplifying memory management for large‑scale VM clusters.

Software ecosystem

• Databases – Systems like Oracle, PostgreSQL, and MySQL that rely on huge shared buffers will see a reduction in page‑table overhead when mapping multi‑terabyte buffers, potentially improving TLB hit rates.
• Containers – Container runtimes that share the host kernel can now allocate more memory per container without hitting the 48‑bit virtual‑address limit, easing the move toward “memory‑first” micro‑services.
• Security tools – The expanded attribute space gives room for future protection‑key extensions, which could enable per‑page encryption keys without extra page‑table walks.

Supply‑chain considerations

Silicon fabs that have already committed to Armv9.2 production lines will need to re‑tool for the extra MMU logic, but the change is largely a micro‑architectural addition rather than a new block. The cost impact is expected to be modest, similar to the transition from 64‑bit to 128‑bit SIMD registers in previous generations. Early‑stage silicon prototypes are already being fabricated on 5 nm EUV processes, suggesting that volume production could begin in H2 2027.

Outlook

FEAT_D128 positions ARM to break the 48‑bit address ceiling that has constrained both server and HPC markets for a decade. While kernel and hypervisor support are still evolving, the groundwork laid by the Linux RFC series provides a clear migration path. As silicon vendors roll out Armv9.3‑based CPUs with the feature enabled, we can expect a measurable shift in memory‑intensive workloads toward ARM platforms, especially where power efficiency and density are critical.

For the full RFC patch series, see the Linux kernel mailing list archive.