Overview
In digital circuits, transistors consume power every time they switch states, which is triggered by the clock signal. Clock gating prevents this switching in idle areas, significantly reducing dynamic power consumption.
How it Works
A 'gate' (logic gate) is added to the clock tree. If a functional block is not needed for the current operation, the gate is closed, and the clock signal stops reaching that block.
Benefits
- Power Efficiency: One of the most effective ways to save power in modern SoCs.
- Reduced Heat: Less switching means less heat generation.
Trade-off
Adds some complexity to the clock distribution network and can introduce small delays when 'waking up' a gated block.