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Memory Consistency Model

A set of rules that defines the order in which memory operations (reads and writes) appear to occur to different processors in a multi-core system.

Categoryhardware

Overview

In a multi-core system, if Core A writes to a location and then Core B reads from it, what value should Core B see? The memory consistency model provides the answer, balancing system performance with ease of programming.

Types

  • Sequential Consistency (SC): The strictest model; all operations appear to happen in a single, global order. Easy to reason about but very slow.
  • Total Store Ordering (TSO): Used by x86; slightly relaxed, allowing some reordering of loads and stores for better performance.
  • Weak/Relaxed Consistency: Used by ARM and RISC-V; allows significant reordering. Provides the best performance but requires programmers to use 'Memory Barriers' to ensure correctness.

Importance

Crucial for the correct operation of multi-threaded software and synchronization primitives like locks and atomics.