Overview
Page tables are managed by the operating system and used by the hardware (MMU) to translate the 'virtual' addresses used by programs into the 'physical' addresses of the RAM chips.
Structure
Modern systems use Multi-level Page Tables (e.g., 4-level or 5-level on x86-64) to efficiently manage large address spaces without requiring massive contiguous blocks of memory for the table itself.
Contents
Each entry (PTE) contains the physical frame number and several status bits (e.g., Present, Writable, User/Supervisor, Dirty).