Overview
Translating a virtual address to a physical address requires looking up entries in a Page Table, which resides in RAM. To avoid this slow memory access for every instruction, the CPU stores recent translations in the TLB.
Mechanism
The TLB is a small, extremely fast associative memory. When the CPU needs to translate an address, it first checks the TLB. A TLB Hit provides the physical address instantly; a TLB Miss requires a slow 'page walk' through the page tables in RAM.
Importance
Without a TLB, the performance of virtual memory systems would be unacceptably slow.