AMD and Intel show giant server sockets for the next AI server cycle

Tom’s Hardware photographed AMD’s SP7 socket and Intel’s LGA9324-1 socket at Computex 2026, giving server buyers a look at the physical platform changes behind the next wave of x86 AI servers.

AMD plans SP7 for 6th Gen EPYC Venice processors, with up to 256 cores, 16 DDR6 memory channels using 12.8 GT/s MRDIMMs, and up to 96 PCIe 6.0 lanes. Intel plans LGA9324-1 for Xeon Diamond Rapids, with up to 192 cores, 16 DDR5 memory channels with MRDIMM support, and PCIe 6.0.

Those numbers explain the socket size. More memory channels require more contacts, more board routing, and more space around the package. PCIe 6.0 also raises signal integrity pressure, which pushes motherboard vendors toward tighter layout rules and higher-cost materials.

Auras showed cooling hardware for both platforms. Tom’s Hardware reported that SP7 can handle CPUs with peak power draw up to 1,400 watts. That figure moves Venice-class systems into a thermal range where liquid cooling shifts from premium option to common rack design choice.

AMD’s platform timing gives it a near-term path to dense dual-socket servers. With two Venice CPUs, server makers could offer up to 512 x86 cores in one system. That density targets cloud providers and AI infrastructure operators that need host CPUs for storage, networking, inference support, and accelerator orchestration.

Intel’s Diamond Rapids platform takes a different route. The 9,324-pin LGA9324-1 socket dwarfs SP7 in physical length, according to Tom’s Hardware’s Computex photos. Intel has not announced base power for Diamond Rapids, but Auras’ water block work points to high-end SKUs that could draw several hundred watts at base and more than 1 kW at peak.

Memory bandwidth sits at the center of both designs. AI servers often pair CPUs with GPUs or accelerators, but the host processor still feeds data, handles preprocessing, manages network traffic, and coordinates storage. Sixteen memory channels give the CPU more bandwidth per socket and help large core counts avoid starvation.

AMD’s reported DDR6 move would mark a platform break from the DDR5 era. DDR6 and MRDIMM support could give Venice more bandwidth headroom, though server builders will need new boards, validated memory, and firmware work. Intel’s Diamond Rapids keeps DDR5 in the reported configuration, which may help memory supply and qualification if DDR6 ramps with limited volume.

PCIe 6.0 matters for accelerator systems. A 64 GT/s link doubles PCIe 5.0 raw transfer rate and helps servers attach GPUs, network cards, storage, and CXL devices without the same lane pressure. The PCI-SIG PCIe specification and CXL standard give vendors a path to memory expansion and cache-coherent device connections, though processor implementation and platform firmware decide what customers can use.

The supply chain challenge now moves to substrates, sockets, boards, coolers, and memory. Large CPU packages need advanced organic substrates with high layer counts. Motherboards need more complex routing around 16 memory channels and PCIe 6.0. Cooling vendors need cold plates that cover huge integrated heat spreaders and keep pressure uniform across the package.

AMD also plans SP8 for systems that need fewer cores and DDR5 channels, according to the report. That split gives server vendors a way to sell lower-cost platforms for workloads that do not need the full SP7 memory and I/O footprint.

The market effect depends on timing. AMD can use SP7 and Venice to pressure Intel in high-density general-purpose servers and AI host nodes in 2026. Intel’s Diamond Rapids, expected for 2027, gives the company a platform reset after its current Xeon roadmap and may carry socket continuity into Coral Rapids.

Server buyers should read the Computex hardware as a platform signal. AMD and Intel plan larger sockets because CPU vendors need more pins for memory, I/O, and power delivery. AI infrastructure has turned the host CPU socket into a board-level engineering problem, and the next server generation will ask data centers to budget for power, cooling, and validation as much as core counts.

Product context: AMD’s current server lineup sits under AMD EPYC, and Intel’s server roadmap belongs to the Intel Xeon family.