AMD Preps Linux Kernel for Zen 6 IBS Enhancements

AMD is laying the groundwork for next-generation Zen 6 processors by enhancing Linux kernel support for Instruction-Based Sampling (IBS) capabilities. A series of patches recently posted to the Linux kernel mailing list have been queued in the tip/tip.git branch, targeting inclusion in Linux 7.1, expected to arrive in April 2026.

The patches focus on expanding the Linux perf subsystem's support for AMD's IBS features, which are particularly relevant for developers and system administrators working with high-performance computing and server workloads. These improvements are expected to debut with Zen 6 processors, likely including the upcoming EPYC Venice server chips.

The new IBS capabilities being introduced include several significant enhancements:

Alternate Disable Bit Implementation AMD is addressing a race condition issue in existing IBS control registers by introducing an alternate disable bit with control-only Model Specific Registers (MSRs). This change eliminates the Read-Modify-Write (RMW) race that can occur in current implementations, providing more reliable control over IBS functionality.

RIP Bit 63 Filtering A new hardware-assisted privilege filtering mechanism allows IBS to operate based on the state of RIP bit 63. This feature enables IBS profiling for unprivileged users without requiring software-based privilege filtering, potentially simplifying security configurations and improving performance for certain use cases.

Fetch Latency Threshold Filter Developers will gain the ability to capture only high-latency fetch events by setting programmable thresholds. This selective sampling reduces noise in performance data and focuses analysis on the most impactful performance bottlenecks.

Streaming-Store Filter The patches add support for sampling only instructions that perform streaming stores. This targeted approach helps developers identify specific code patterns that may benefit from optimization or different memory access strategies.

Remote Socket Indicator For multi-socket systems, AMD is introducing the ability to indicate data sources from remote sockets for load/store instructions. This feature provides crucial visibility into NUMA (Non-Uniform Memory Access) behavior and helps optimize memory access patterns in large-scale deployments.

These enhancements represent AMD's continued investment in providing deep hardware-level insights for performance analysis. The Linux perf subsystem integration ensures that these capabilities will be readily available to developers and system administrators without requiring custom tools or workarounds.

The timing of these patches aligns with AMD's typical processor release cadence, with Zen 6 expected to arrive in 2026. The patches being in the tip/tip.git perf/core branch indicates they're on track for the Linux 7.1 merge window, suggesting AMD is coordinating closely with the kernel development community to ensure seamless support for their next-generation hardware.

For developers working on performance-critical applications, especially in the HPC and enterprise segments where EPYC processors dominate, these IBS improvements will provide more granular control over profiling and analysis. The ability to filter events based on specific criteria like latency thresholds and instruction types means developers can focus their optimization efforts on the most impactful areas of their code.

The patches also demonstrate AMD's commitment to Linux as a first-class platform for their hardware. By working with the kernel community to upstream these features, AMD ensures broad compatibility and support across distributions, benefiting both enterprise users and the open-source ecosystem as a whole.

As Zen 6 processors approach release, these kernel enhancements will be crucial for developers looking to leverage the full capabilities of AMD's latest architecture. The combination of hardware improvements and software support represents the kind of ecosystem maturity that has helped AMD gain significant market share in the server and high-performance computing segments.