AMD Zen 6 'Venice' Engineering Samples Break Cover with Up to 192 Coars in Early Stress Tests

Engineering samples of AMD's upcoming Zen 6 architecture, codenamed Venice, have surfaced in early stress tests, revealing configurations with up to 192 cores. These preliminary benchmarks provide the first concrete evidence of AMD's next-generation CPU design, which appears to focus on core density improvements and memory bandwidth enhancements for the datacenter market.

Platform Configurations and Core Counts

The six engineering samples were tested across three different AMD platforms codenamed Congo, Kenya, and Nigeria, with varying core counts and configurations:

• Congo Platform: Two chips tested

  • Sample 100-000001053-03: 192 cores, 8 CCDs, 2 IODs
  • Sample 100-000001863-02: 64 cores, 2 CCDs, 2 IODs

• Kenya Platform: One chip tested

  • Sample 100-000001056-09: 128 cores, 4 CCDs, 2 IODs

• Nigeria Platform: Three dual-CPU configurations tested

  • Sample 100-000002138-02: 64 cores (2×32-core CCDs), 2 IODs per CPU
  • Sample 100-000001056-03: 128 cores (2×4 CCDs), 2 IODs per CPU
  • Sample 100-000001051-08: 192 cores (2×8 CCDs), 2 IODs per CPU

Core Density Improvements

The most significant revelation from these engineering samples is the substantial increase in core density per CCD compared to AMD's current Zen 5 architecture:

• 64-core and 128-core models feature 32 cores per CCD
• 192-core configurations use 24 cores per CCD

These specifications align with previous industry reports suggesting that Zen 6 will offer two core variants:

1. Zen 6 standard cores: Reportedly housed in 12-core CCDs
2. Zen 6c cores: Space-optimized cores housed in 32-core CCDs

The presence of 32-core CCDs in the leaked samples strongly indicates that AMD is utilizing Zen 6c cores in these engineering samples. This approach mirrors AMD's previous strategy with Zen 4c, which focused on performance-per-watt and core density for specific workloads.

Performance Metrics

While limited performance data is available from these early engineering samples, one 64-core chip achieved a peak clock speed of 3.54GHz during stress testing. This clock speed is consistent with expectations for early engineering samples, which typically prioritize stability over maximum performance.

Architecture Enhancements

Based on the leaked information and industry reports, Zen 6 'Venice' will introduce several significant improvements over the current generation:

• Memory Bandwidth: Substantial improvements to memory bandwidth compared to the current Turin generation
• L3 Cache: Alleged increase to 48MB L3 cache capacity
• Socket: Venice will utilize AMD's upcoming SP7 socket
• Maximum Core Count: Up to 256 cores for flagship datacenter parts

Market Positioning and Release Timeline

AMD has officially committed to a 2026 release for Venice, the datacenter implementation of Zen 6. However, the company has not announced a timeline for consumer platforms, codenamed Olympic Ridge. This departure from AMD's traditional release strategy—where consumer CPUs typically debut before datacenter variants—suggests the company is prioritizing the datacenter market with Zen 6.

Several factors may explain this strategic shift:

1. Renewed demand in the datacenter sector following recent supply chain adjustments
2. Competitive positioning against Intel's upcoming Granite Rapids platform
3. Opportunity to establish leadership in high-core-count server markets

The leaked engineering samples indicate that AMD is focusing on core density as a key differentiator. With configurations offering up to 192 cores in early samples and plans for 256-core flagship parts, AMD appears to be targeting the high-end server market where core count remains a critical purchasing factor.

Competitive Analysis

The Zen 6 architecture's emphasis on core density positions AMD to compete effectively against Intel's upcoming Granite Rapids platform, which is expected to feature similar core count improvements. However, Intel's approach with Granite Rapids reportedly includes a hybrid core design with both Performance-cores and Efficient-cores, similar to their consumer strategy.

AMD's focus on optimizing both standard Zen 6 and Zen 6c cores suggests a more nuanced approach to workload-specific optimization. The 32-core CCDs in the leaked samples indicate significant improvements in core density, which could translate to better performance-per-watt in datacenter environments where power efficiency remains a critical concern.

Supply Chain Implications

The emergence of these engineering samples across multiple platforms (Congo, Kenya, and Nigeria) suggests AMD has progressed significantly in the development cycle. The variety of configurations indicates a comprehensive validation process across different market segments and use cases.

The presence of dual-CPU configurations on the Nigeria platform specifically indicates that AMD is preparing for multi-socket server deployments, which remain critical in the datacenter market. The consistent 2 IOD (Input/Output Die) configuration across all samples suggests a standardized approach to I/O handling regardless of core count.

Future Outlook

As these engineering samples represent early silicon, final specifications and performance characteristics may vary. However, the core density improvements and architectural enhancements suggest that Zen 6 will represent a significant evolution from the current Zen 5 generation.

The absence of consumer platform (Olympic Ridge) information in these leaks leaves questions about how AMD will implement Zen 6 in desktop and laptop markets. Traditionally, consumer variants have featured lower core counts than their datacenter counterparts, but the emphasis on core density in these early samples suggests AMD may carry over some of these optimizations to consumer products.

Industry analysts will be watching for AMD's official announcements regarding Zen 6, particularly as the company approaches its stated 2026 release window for Venice. The performance and efficiency improvements demonstrated in these engineering samples could set the stage for another competitive cycle in the server CPU market.