IBM and Lam Research Partner to Pioneer Sub-1nm Chip Manufacturing with High-NA EUV and Dry Resist Technology

IBM and Lam Research have established a five-year research partnership focused on developing the materials and fabrication processes required to scale logic chips beyond the 1nm node. The collaboration leverages Lam's Aether dry resist technology in conjunction with high-NA EUV lithography, with research activities centered at IBM Research's NY Creates Albany NanoTech Complex in New York.

The technical effort will integrate multiple Lam platforms, including the Kiyo and Akara etch systems, Striker and ALTUS Halo deposition systems, and the centerpiece Aether dry resist technology. This collaboration builds on more than a decade of joint work between the companies, which previously contributed to 7nm process development, nanosheet transistor architecture, and early EUV process integration. Notably, IBM unveiled what it described as the world's first 2nm node chip in 2021, demonstrating the effectiveness of their ongoing partnership.

Under the new agreement, researchers will focus on validating complete process flows for nanosheet and nanostack device architectures, along with backside power delivery technologies. These advanced approaches represent critical innovations for sub-1nm manufacturing, where traditional design methodologies face fundamental physical limitations.

Technical Advantages of Aether Dry Resist

Standard EUV lithography relies on chemically amplified resists applied via spin coating and developed using wet chemistry. This approach encounters a fundamental limitation at the smaller geometries that high-NA EUV scanners are designed to print: stochastic noise. This statistical variation in photon absorption per unit area drives defect rates higher as features continue to shrink.

Lam's Aether process circumvents these wet chemistry limitations by depositing resist through vapor-phase precursors and developing it using plasma-based dry processes. According to Lam, its metal-organic compounds absorb three to five times more EUV light than conventional carbon-based resist materials. This increased absorption reduces the exposure dose required per wafer pass, maintaining the viability of single-print patterning at nodes where wet-process alternatives would necessitate more expensive multi-patterning approaches.

The dry resist process also reduces the number of steps between exposure and etch, minimizing points at which pattern fidelity can degrade. This advantage becomes increasingly critical as geometries continue to tighten and process windows narrow.

The IBM-Lam collaboration specifically targets proving that Aether can reliably transfer high-NA EUV patterns into actual device layers at production yield levels—a prerequisite before sub-1nm processes can advance toward commercial manufacturing.

Device Architecture Innovations

The partnership will focus on several advanced transistor architectures essential for sub-1nm manufacturing:

1. Nanosheet transistors: These devices stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint. This approach helps maintain performance improvements while addressing the leakage current challenges that emerge at extremely small scales.

2. Nanostack devices: An evolution of nanosheet technology that further optimizes current flow and electrostatic control.

3. Backside power delivery: This innovative approach routes power connections through the back of the wafer rather than the front, freeing up front-side metal layers for signal routing. It also reduces resistance losses that compound at high transistor densities—a critical consideration as power delivery becomes increasingly challenging at advanced nodes.

Strategic Context for Lam Research

The IBM announcement represents the third significant Aether-related development Lam has pursued in the past 14 months. In January 2022, Lam confirmed that an unnamed leading memory manufacturer had selected Aether as the production tool of record for its most advanced DRAM processes. Then, in September 2022, Lam established a cross-licensing and collaboration agreement with JSR Corporation and its subsidiary Inpria, integrating JSR's metal oxide resists and patterning materials with Lam's etch, deposition, and dry resist capabilities specifically for high-NA EUV applications.

These moves demonstrate Lam's strategic approach to building a comprehensive dry resist ecosystem ahead of wider high-NA EUV adoption. ASML began shipping its first high-NA EUV systems in 2023, and as these tools move toward broader foundry adoption, the choice of resist process will become one of the most consequential materials decisions chipmakers face.

JSR and Inpria's expertise in metal oxide resists complements Lam's vapor deposition approach, providing coverage across both dry resist and metal oxide patterning materials for sub-1nm manufacturing.

Lam faces competition in this space, with Applied Materials developing its own patterning materials and process integration capabilities. ASML's dominant position in lithography also gives it natural influence over how the resist ecosystem develops around its tools. Lam's partnerships with IBM and JSR/Inpria represent an effort to establish dry resist as the default process integration path before tooling decisions become embedded within foundries.

Manufacturing Timeline and Industry Impact

IBM's Albany NanoTech Complex serves as a process development facility rather than a production fab, meaning the collaboration will produce validated process flows and materials knowledge that commercial foundries can adopt. This model mirrors the companies' prior successful work on 7nm and nanosheet technologies, where research demonstrated at Albany eventually fed into production processes at TSMC and other manufacturers.

Based on this historical pattern, sub-1nm process work commencing in 2026 is unlikely to reach volume manufacturing before the early 2030s. This extended timeline reflects the significant engineering challenges involved in transitioning from research demonstrations to high-volume production at these extreme scales.

For Lam Research, this collaboration presents substantial commercial potential. If Aether becomes the validated dry resist solution for high-NA EUV logic manufacturing, Lam stands to add a significant new revenue category beyond the etch and deposition tools it already supplies to nearly every advanced chipmaker. The five-year commitment with IBM builds crucial process familiarity and customer confidence well before foundries make resist process decisions for their sub-1nm nodes.

Lam's commercial customers—including TSMC, Samsung, Intel, and others—will ultimately adopt whatever process knowledge emerges from Albany through this research effort. The success of this collaboration could therefore influence the direction of semiconductor manufacturing for the remainder of this decade and beyond.