Intel starts 18A-P risk production with a 9% speed gain

Intel has started risk production for 18A-P, a performance-focused update to its 18A manufacturing process, after giving VLSI 2026 attendees more detail on the node. Intel says 18A-P raises performance by 9% at the same power or cuts power by 18% at the same performance, based on a standard Arm core subblock running at 0.75 volts.

Risk production puts full wafers on a standard production line at low volume. Intel engineers use that stage to measure defect density, speed, leakage, and process variation before they commit capacity to high-volume manufacturing. New advanced logic nodes often spend 12 to 24 months in that phase, but 18A-P builds on 18A, so customers should expect a shorter path than a clean-sheet node would require.

Intel designed 18A-P as a drop-in upgrade for 18A. Designers can move 18A layouts to 18A-P without redesigning the chip, because Intel kept the same cell libraries at 180 nanometers for high performance and 160 nanometers for high density. Teams that want more speed or lower leakage can use new device options, but Intel does not require that work for migration.

That compatibility matters for Panther Lake, Xeon 6+ and future external foundry customers. Intel already uses 18A for those internal products, and the company wants Intel Foundry to win outside designs from companies that need advanced-node capacity outside Taiwan. A process update that improves speed without forcing a full physical design reset gives Intel a stronger pitch to customers weighing cost, schedule, and supply risk.

The technical shift starts with new transistor options. Intel added W1 support to the 180-nanometer library, W1.5 to the 160-nanometer library and W3P to both libraries. W1 and W1.5 target lower-power designs with narrower devices and lower capacitance. W3P targets higher drive current.

W3P carries Intel’s Power Boost design. Intel’s 18A already uses PowerVia, a backside power delivery method that routes power through the back of the wafer. That frees the front side for signal wiring and cuts voltage loss in dense logic. W3P adds contacts on the front and back side, reducing parasitic resistance and allowing the transistor to switch faster.

Intel also added a threshold-voltage option called ULVTLL, short for ultra-low voltage threshold low leakage. Designers already balance high, standard, low and ultra-low threshold voltage devices to trade speed against leakage. ULVTLL gives them another point between low-threshold and ultra-low-threshold devices, with more performance than LVT and less leakage than ULVT.

Those options give chip teams more room to tune hot blocks. A CPU core, graphics tile, cache slice, fabric router or AI accelerator may need different transistor mixes. Intel can now offer 18A-P customers more choices inside the same design rules instead of asking them to wait for a later node.

Intel also claims 18A-P reduces thermal resistance by 20% to 40% and cuts via resistance by 10% to 30% on performance-critical layers. Lower thermal resistance helps heat leave dense logic faster, which can sustain higher boost clocks or reduce cooling pressure. Lower via resistance helps power and signals move through the stack with less loss.

The supply-chain angle gives 18A-P more weight than a normal process update. TSMC still dominates leading-edge foundry manufacturing, and its Arizona investment will add U.S. capacity. Intel needs its own U.S. fabs to prove yield, performance and customer readiness at the same time. The company says 18A defect rates keep falling as it ramps two U.S. fabs.

Intel’s challenge now moves from slides to wafers. Risk production will tell customers whether 18A-P can deliver the promised speed, power and thermal gains across real product designs. If Intel keeps the migration path smooth from 18A, the company can give Panther Lake, Xeon 6+ and outside customers a stronger manufacturing option before its next full node arrives.