Linux 7.0 Adds AMD Zen 5 CXL Address Translation Support

The Linux 7.0 kernel has merged a significant feature for AMD EPYC Zen 5 server platforms: ACPI PRMT-based address translation for the Compute Express Link (CXL) subsystem. This long-awaited capability, which went through ten rounds of code review over several months, is now upstream and ready for production use.

What Is CXL Address Translation?

Compute Express Link is a high-speed interconnect standard designed for memory expansion and device connectivity in data centers. On AMD Zen 5 systems, the platform may be configured to use "Normalized addresses," where host physical addresses (HPAs) differ from system physical addresses (SPAs).

In this configuration, CXL endpoints have their own physical address space, and incoming HPAs are already converted to the device's physical address (DPA). This means endpoints have interleaving disabled and are programmed for passthrough mode where DPA equals HPA.

However, host physical addresses still need translation from the endpoint to its CXL host bridge to identify the endpoint's root decoder and region address range. This is where the ACPI Platform Runtime Mechanism (PRM) comes in, providing a handler to translate DPA to SPA.

Technical Implementation

The implementation introduces a new file, core/atl.c, to handle ACPI PRM-specific address translation code. The naming is loosely related to the kernel's AMD Address Translation Library (CONFIG_AMD_ATL), but the implementation doesn't depend on it and isn't vendor-specific.

The code uses Kbuild and Kconfig options to enable functionality based on architecture and platform options. AMD Zen 5 systems support the ACPI PRM CXL Address Translation firmware call, as specified in the ACPI v6.5 Porting Guide under "Address Translation - CXL DPA to System Physical Address."

Documentation and Future Support

Alongside the core implementation, a separate documentation patch went through five rounds of review. This documentation provides detailed coverage of ACPI PRM CXL Address Translation, helping developers understand and work with the new feature.

While this capability debuted with the AMD EPYC 9005 series processors, it's expected to continue being built upon in next-generation EPYC Zen 6 platforms. The late arrival in the mainline kernel means Linux 7.0 will be the first stable release to fully support this feature, but it positions the kernel well for future AMD platform developments.

Additional CXL Improvements

The CXL merge for Linux 7.0 also includes CXL port error protocol handling and reporting additions, along with various code clean-ups and fixes. These improvements round out the CXL support in the kernel, making it more robust for production deployments.

The feature is particularly important for data center operators running AMD EPYC 9005 series systems, as it enables proper memory mapping and device communication through CXL interconnects. With this support now merged, Linux distributions can begin integrating the functionality into their kernels, bringing full CXL capabilities to Zen 5 platforms.