Overview
The LSU manages the interface between the CPU's registers and the memory hierarchy (cache and RAM). It handles the complexities of memory addressing and ensures that data is moved correctly and efficiently.
Key Tasks
- Address Calculation: Working with the AGU to determine the physical memory address.
- Memory Access: Sending requests to the L1 data cache.
- Data Alignment: Handling cases where data is not perfectly aligned with memory boundaries.
- Ordering: Ensuring that memory operations happen in a way that maintains the memory consistency model.
Performance
Because memory access is slow, the LSU often includes buffers (Load/Store buffers) to allow the CPU to continue working while waiting for data.