Aegis: The First Truly Open-Source FPGA From Silicon to Toolchain

The world of FPGAs has long been dominated by proprietary solutions from established players like Xilinx, Intel, and Lattice. These companies control not only the software toolchains but also the underlying silicon architectures, creating barriers to entry and limiting innovation. Now, a new project called Aegis is attempting to change this paradigm by creating a fully open-source FPGA, starting from the silicon itself.

What Makes Aegis Different

Existing open-source FPGA efforts have typically focused on either reverse-engineering proprietary architectures (like Project IceStorm and Apicula) or building tooling around closed silicon (like Yosys and nextpnr). What sets Aegis apart is its comprehensive approach: the fabric design is open, the toolchain is open, and the path to real silicon goes through open PDKs (Process Design Kits) and shuttle services like wafer.space.

This represents a fundamental shift in the open-source hardware movement. Rather than working around proprietary limitations, Aegis aims to create an entirely open ecosystem that can compete with established commercial solutions.

Technical Architecture

The Aegis project generates parameterized FPGA devices with a complete set of essential components:

• LUT4: Approximately 2,880 Look-Up Tables with 4 inputs
• BRAM: 128 tiles of dual-port 128x8 block RAM
• DSP: 64 tiles of 18x18 multiply-accumulate units
• I/O: 224 bidirectional pads
• SerDes: 4 protocol-agnostic serializer/deserializer tiles
• Clock management: 2 tiles with 8 outputs total and phase control
• Routing: 4 tracks per edge for interconnect

The architecture follows Xilinx-style conventions but is implemented from scratch using open methodologies. The FPGA fabric is generated by ROHD (a Dart HDL framework) and outputs synthesizable SystemVerilog, making it compatible with standard FPGA design flows.

The First Device: Terra 1

The inaugural Aegis device, dubbed "Terra 1," targets the GlobalFoundries 180nm MCU process (GF180MCU) through wafer.space, an open silicon shuttle service. This choice of process node balances accessibility with performance, making it suitable for a wide range of applications while keeping manufacturing costs reasonable.

Complete Toolchain

Unlike many open-source FPGA efforts that focus only on specific tools, Aegis provides a complete toolchain for each device:

1. Synthesis: Using Yosys with Aegis-specific cells and technology maps
2. Place and route: Via nextpnr-aegis, customized for the Terra 1 architecture
3. Bitstream generation: Using terra_1-pack to convert placed routes to a bitstream
4. Simulation: With terra_1-sim for verifying designs before deployment

This comprehensive toolchain enables designers to take Verilog code all the way through to a working FPGA implementation, just like with commercial solutions.

ASIC Tapeout Pipeline

Perhaps most significantly, Aegis includes a complete pipeline for taping out the FPGA fabric itself to a foundry. This means the project doesn't just provide tools for using FPGAs—it provides the means to manufacture them as well. The tapeout pipeline synthesizes the FPGA fabric to PDK standard cells, producing:

• Gate-level netlist (Yosys)
• Placed & routed layout (OpenROAD)
• GDSII file for foundry submission
• Layout visualization
• Timing analysis reports
• Power consumption estimates

This capability positions Aegis as a complete solution for both FPGA users and those who want to create or customize FPGA hardware.

Configuration Architecture

The Aegis architecture uses a serial shift register chain for configuration, loading data in a specific order: clock tiles → IO tiles → SerDes tiles → fabric tiles (in row-major order). Each component has a specific configuration bit width:

• CLB: 18 bits (LUT4 + D flip-flop + MUXCY carry chain)
• Tile: 46 bits (CLB + 4-directional routing muxes)
• BRAM: 8 bits (dual-port 128x8 block RAM)
• DSP: 16 bits (18x18 multiply-accumulate with optional pipeline)
• IO: 8 bits (bidirectional pad with input/output registers)
• SerDes: 32 bits (protocol-agnostic serializer/deserializer)
• Clock: 49 bits (4-output clock divider with phase control)

Building and Development

The project uses Nix with flakes for building and development, a modern approach that ensures reproducible builds and manages dependencies effectively. This choice reflects the project's commitment to contemporary software development practices applied to hardware design.

Significance and Potential Impact

Aegis represents a significant milestone in the open-source hardware movement. If successful, it could:

1. Democratize access to FPGA technology by removing proprietary barriers
2. Increase transparency and security by eliminating black boxes in FPGA architectures
3. Enable customization of FPGA architectures for specific applications
4. Lower barriers to entry for FPGA development and education
5. Create opportunities for innovation in specialized FPGA architectures

The project's approach of using open PDKs and shuttle services like wafer.space also highlights a broader trend in hardware development—leveraging shared infrastructure to reduce costs and increase accessibility.

Challenges and Future Directions

Creating a complete open-source FPGA stack is an enormous undertaking. The project will need to address several challenges:

• Proving the silicon works reliably across various applications
• Achieving performance comparable to established commercial FPGAs
• Building a community around the project
• Ensuring compatibility with existing FPGA design methodologies
• Potentially scaling to more advanced process nodes

Despite these challenges, Aegis represents an ambitious and important step toward more open, transparent, and accessible hardware. The project's GitHub repository (https://github.com/MidstallSoftware/aegis) provides detailed documentation and build instructions for those interested in exploring or contributing to this effort.

As hardware becomes increasingly central to technology innovation, projects like Aegis play a crucial role in ensuring that the tools and infrastructure remain accessible to everyone, not just those who can afford proprietary solutions.