Intel Nova Lake Die Sizes Leak, Signaling Higher Cost — Smaller Compute Tile Still Demands Higher Price on TSMC N2

Intel's upcoming Core Ultra series 4 processors, codenamed Nova Lake, are shaping up to be a significant leap in performance for the company's desktop and laptop offerings. However, leaked die size information suggests these chips will come with a hefty manufacturing price tag that could impact their market positioning.

According to leaked information from @9550pro, when implemented on TSMC's N2 manufacturing technology, Nova Lake's compute tile with eight high-performance Coyote Cove P-cores and 32 energy-efficient Arctic Wolf E-cores measures over 110 mm². The same tile equipped with 144 MB of big last-level cache (bLLC) balloons to over 150 mm² in size.

For context, Arrow Lake's compute tile—implemented on TSMC's N3B technology and housing eight Lion Cove P-cores and 16 Skymont E-cores—is believed to be around 117 mm². This means the base Nova Lake compute tile without bLLC is actually smaller than its predecessor, but the manufacturing costs tell a different story.

TSMC's N2 process is projected to be more expensive than N3B despite featuring roughly the same number of EUV layers (20-23). The increased cost stems from EUV multipatterning requirements for critical layers, which adds significant complexity and expense to the manufacturing process. This, combined with other factors, means Nova Lake's compute tile without bLLC will likely be more expensive to produce than Arrow Lake's tile, assuming the leaked die sizes are accurate.

The compute tile with bLLC will be significantly more expensive, though Intel appears prepared for this reality. These tiles will be used in high-end CPUs aimed at gamers and enthusiasts, where the target market is less price-sensitive and more focused on performance.

Like most of Intel's recent processors, Nova Lake will employ a multi-tile design including a compute tile (or two), a system-on-chip (SoC) tile, a GPU tile, an I/O tile, and a base tile. Interestingly, the main compute tile will be manufactured using two different processes: Intel's own 18A fabrication technology at the company's Fab 32 in Arizona, and TSMC's N2 process at the foundry's Fab 22 in Taiwan.

Intel has not publicly disclosed which Nova Lake versions will be used for desktops versus laptops, or whether there will be any differences between them. However, given that Intel expects to make the majority of Nova Lake silicon in-house and considering that laptop CPUs currently outsell desktop CPUs at a 7:3 ratio, it's reasonable to expect that the bulk of laptop CPUs will be manufactured at Intel's Arizona facility.

This dual-source strategy could help Intel manage costs and supply chain risks. The company's balance sheet will barely suffer from the high costs of Nova Lake compute tiles with bLLC at TSMC, as the majority of production will occur at Intel's own facilities.

It's worth noting that chip cost is a function of multiple factors beyond just process technology and die size, including functional yield and parametric yield. While we can speculate that TSMC's N2 is more expensive than N3B, without concrete data on parametric yields, any assumptions about the actual costs of the compute tile remain highly speculative.

The Nova Lake architecture represents Intel's continued push to regain competitiveness in the CPU market, particularly against AMD's Ryzen series. With its combination of high-performance P-cores and energy-efficient E-cores, Nova Lake aims to deliver the kind of performance gains that could finally put Intel back in contention for the performance crown in both desktop and laptop segments.

However, the leaked die sizes and manufacturing costs suggest that this performance won't come cheap. Whether Intel can translate these technical achievements into market success will depend not just on raw performance, but also on how well they can manage the cost structure and position these chips in an increasingly competitive market.

The use of TSMC's advanced N2 process for some Nova Lake variants also highlights Intel's pragmatic approach to manufacturing, leveraging external foundries when it makes strategic sense while simultaneously investing in its own process technology development. This hybrid approach may become increasingly common as semiconductor manufacturing becomes more complex and expensive with each successive node.