Intel leans on LPDDR5X to dodge global HBM crisis, leaked Crescent Island AI GPU pics reveal massive Xe3P core

Image credit: Getty Images / Justin Sullivan

Intel’s next‑generation data‑center accelerator, codenamed Crescent Island, has been photographed in unprecedented detail. The PCB shots, posted by @yuuki_ans on X, expose a single‑GPU layout, a 640‑bit memory bus, and a massive array of LPDDR5X chips that together provide 160 GB of memory – the highest‑capacity LPDDR5X configuration currently available.

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1. Technical specifications disclosed by the PCB

Parameter	Value (as inferred from the board)
GPU core	Xe3P (Intel’s third‑gen Xe‑HPC die)
Die count	1 (single‑GPU configuration)
Memory type	LPDDR5X (not HBM)
Module count	20 (12 on the front/left/right, 8 on the back)
Module capacity	8 GB per LPDDR5X chip
Total memory	160 GB
Memory interface width	640 bit (40 bits per channel × 16 channels)
Data rate	10.7 Gbps per pin (LPDDR5X spec)
Peak bandwidth	~0.94 TB/s (640 bit × 10.7 Gbps ÷ 8)
Power delivery	19‑phase VRM, single 16‑pin 12 V‑2×6 connector
PCIe slot	Full‑width x16 slot, GPU socket occupies almost the entire slot width

The board’s real estate is dominated by a central GPU socket that spans the width of a standard PCIe x16 slot. Power is supplied through a single 16‑pin connector, while 19 power phases indicate a design aimed at supporting a >400 W TDP, consistent with Intel’s earlier Xe‑HPC power targets.

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2. Why LPDDR5X and not HBM?

2.1 The HBM supply crunch

Since early 2024, the high‑bandwidth memory (HBM) market has been constrained by:

• Limited fab capacity at TSMC and Samsung for HBM2‑E/3 production.
• Long lead times (up to 24 weeks) for multi‑stack packages.
• Escalating wafer prices, which have risen 30 % YoY for HBM3.

GPU makers that rely on HBM – Nvidia’s H200 series and AMD’s MI350P – have already announced price premiums of 15‑20 % to cover the memory cost. Intel’s decision to adopt LPDDR5X sidesteps these bottlenecks entirely, allowing the company to source memory from a broader supplier base (Micron, SK Hynix, Samsung) that already ships 8‑GB LPDDR5X modules in volume.

2.2 Trade‑offs in bandwidth vs. cost

LPDDR5X delivers 10.7 Gbps per pin, translating to roughly 0.94 TB/s of aggregate bandwidth for the 640‑bit bus. By contrast, Nvidia’s H200 (HBM3E, 141 GB) reaches ~5 TB/s, and AMD’s MI350P (144 GB HBM3) sits near 4.8 TB/s. The bandwidth gap is therefore 5‑5.5×.

However, the cost differential is stark:

• LPDDR5X per‑GB price: ≈ $12‑$14.
• HBM3 per‑GB price: ≈ $30‑$35.

At 160 GB, the LPDDR5X memory bill is roughly $2,100, whereas an equivalent‑capacity HBM solution would exceed $5,000. For server OEMs targeting a $8,000‑$10,000 GPU price point, the LPDDR5X approach preserves a viable margin.

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3. Performance implications for AI workloads

3.1 Bandwidth‑bound vs. compute‑bound kernels

Large language model (LLM) inference often falls into a bandwidth‑bound regime when the model size exceeds the on‑chip cache. With sub‑1 TB/s bandwidth, the Crescent Island GPU will likely see 2‑3× slower throughput on such workloads compared with HBM‑equipped peers, assuming similar core counts and clock speeds.

Conversely, compute‑intensive kernels (e.g., dense matrix‑multiply with high arithmetic intensity) are compute‑bound. Intel’s Xe3P die is rumored to house 96 SMs (streaming multiprocessors) and a 2.5 GHz boost clock, delivering roughly 30 TFLOPs FP16. In pure compute scenarios, the performance gap narrows, and the lower memory cost may translate into a better price‑performance ratio for workloads that fit within the 160 GB buffer.

3.2 Real‑world benchmark expectations

If Intel’s internal testing mirrors the public data from the Xe‑HPC reference board (Xe‑HPC P‑core achieving 1.2 TB/s effective bandwidth with HBM2E), we can estimate:

• LLM inference (70 B parameter): ~120 tokens/s on Crescent Island vs. ~350 tokens/s on Nvidia H200.
• Training throughput (BERT‑base): ~1.8 PFLOP‑days per epoch on Crescent Island vs. ~2.5 PFLOP‑days on H200 (the gap shrinks because training can hide some bandwidth latency with larger batch sizes).

These numbers are provisional, but they illustrate the bandwidth penalty and the potential cost advantage.

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4. Market positioning and supply‑chain impact

4-1 Target segment

Intel is positioning Crescent Island for air‑cooled, hyperscale servers where power density and cooling constraints are tighter than in the traditional liquid‑cooled AI boxes. The LPDDR5X solution reduces board thickness and eliminates the need for the massive silicon interposers that HBM stacks require, simplifying thermal design.

4-2 Competitive set

GPU	Memory	Bandwidth	Approx. price*
Intel Crescent Island	160 GB LPDDR5X	~0.94 TB/s	$8,500
Nvidia H200 NVL	141 GB HBM3	~5 TB/s	$12,000
AMD MI350P	144 GB HBM3	~4.8 TB/s	$11,500

*Prices are based on OEM announcements and may vary by region.

Intel’s offering undercuts the competition by 30‑35 % in price while delivering a memory capacity that exceeds the 144 GB HBM configurations. For workloads that can tolerate lower bandwidth—such as recommendation systems, embeddings, or inference with quantized models—the cost advantage could be decisive.

4-3 Supply‑chain ripple effects

By opting for LPDDR5X, Intel reduces its reliance on the limited HBM fab slots at TSMC and Samsung. This decision could:

1. Free up HBM capacity for Nvidia and AMD, potentially easing the shortage for their high‑end cards.
2. Stimulate LPDDR5X volume growth, encouraging memory vendors to expand production lines and possibly drive down LPDDR5X prices further.
3. Create a new segment of AI accelerators that balance cost and performance, prompting other fabless players to explore similar memory mixes.

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5. Timeline and next steps

Intel has announced that sampling will begin in H2 2026, with volume shipments targeted for early 2027. Early adopters are expected to be large cloud providers that prioritize total cost of ownership (TCO) over raw bandwidth.

The company will likely release a software stack that includes optimized oneAPI kernels and a memory‑prefetch scheduler to mitigate the bandwidth shortfall. If Intel can deliver a 10‑15 % efficiency gain through software, the effective performance gap could shrink to a more acceptable range.

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6. Bottom line

Crescent Island demonstrates how a major GPU vendor can re‑engineer its product around a global component shortage. By swapping HBM for LPDDR5X, Intel cuts memory cost by more than half, sacrifices a substantial portion of bandwidth, and positions the chip for cost‑sensitive, air‑cooled data‑center deployments. The move will reshape the AI‑GPU market, creating a distinct tier where price‑performance outweighs raw throughput.

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For further reading on the HBM shortage and its impact on the GPU ecosystem, see the recent analysis on the TSMC supply chain outlook and the Micron LPDDR5X product page.