Peking University Unveils 3D EDA Tool for Huawei’s LogicFolding Architecture

Announcement

Peking University’s School of Integrated Circuits has released a prototype electronic‑design‑automation (EDA) platform built expressly for Huawei’s LogicFolding architecture. The tool was announced two days after Huawei presented the LogicFolding concept and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai.

The university’s prototype claims a 30 % reduction in total internal wire length for open‑source benchmark circuits, along with measurable improvements in both performance and thermal management when compared with traditional 2‑D design flows.

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Technical specifications

True‑3D design methodology

Conventional advanced‑node design treats each metal layer as a separate 2‑D plane. Designers place and route the circuit on one layer, then repeat the process for the next, finally stacking the layers in a back‑end process. LogicFolding flips this paradigm: the layout is folded vertically during the front‑end design stage, allowing transistors and interconnects to occupy multiple stacked layers as a single, continuous design space.

Key technical shifts include:

Aspect	Conventional flow	LogicFolding flow
Design space	2‑D per metal layer, later stacked	3‑D volumetric space from the start
Placement algorithm	Optimizes within a single plane	Simultaneously optimizes across all vertical levels
Wire routing	Separate routing per layer, then via insertion	Unified routing that minimizes total path length
Signal delay	Dominated by inter‑layer vias and long horizontal runs	Shorter vertical paths cut resistance (R) and capacitance (C) → lower RC delay

Reported metrics

• Wire length: 30 % shorter than the same netlist routed with Synopsys IC Compiler II on a 7 nm baseline.
• Critical‑path delay: 12 % reduction on the open‑source CoreMark benchmark.
• Power density: 8 % lower hotspot temperature in thermal simulations using ANSYS Icepak, attributed to reduced IR drop and tighter vertical heat paths.

The prototype integrates a custom place‑and‑route engine with a vertical constraint solver, built on top of the open‑source OpenROAD framework. Process‑design‑kit (PDK) data for a 7 nm node (provided by a Chinese foundry partner) was imported to enable realistic parasitic extraction.

Comparison with existing 3‑D IC tools

Major EDA vendors—Synopsys, Cadence, Siemens EDA—offer 3‑D IC platforms that focus on chiplet‑level stacking (e.g., interposer, TSV, fan‑out wafer‑level packaging). Those tools assume each die is already fully placed in 2‑D before being bonded together. LogicFolding, by contrast, performs intra‑die vertical folding at the transistor level, a more granular optimization that requires a fundamentally different algorithmic approach.

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Market implications

Strategic relevance for Huawei

Huawei has set a target of 1.4 nm‑equivalent transistor density by 2031 without relying on EUV lithography, which is restricted under U.S. export controls. LogicFolding is a core pillar of that roadmap because vertical stacking can effectively increase transistor density without shrinking the lithographic pitch. The first commercial deployment is slated for the upcoming Kirin X2 smartphone processor, which will be the inaugural chip to ship with LogicFolding.

Impact on the Chinese EDA ecosystem

Globally, Synopsys, Cadence, and Siemens command 31 %, 30 % and 13 % of the EDA market, respectively, and together hold over 80 % of the Chinese market share (EE Times China). The U.S. briefly lifted EDA export restrictions last year, but the episode underscored China’s reliance on Western tools for advanced‑node design.

Peking University’s prototype demonstrates a potential domestic alternative for the digital design flow at advanced nodes. If the university can mature the tool into a production‑grade suite—integrating full PDK support, verification, and sign‑off—Chinese fabs could reduce their exposure to export‑control volatility.

Timeline and hurdles

A university prototype is still several years away from commercial readiness. Critical steps include:

1. Process‑design‑kit integration with multiple foundries (e.g., SMIC, Yangtze Memory).
2. Verification at volume – thousands of tape‑outs are needed to prove reliability.
3. Ecosystem support – standard cell libraries, IP blocks, and design‑for‑test (DfT) flows must be adapted to the 3‑D model.
4. Tool certification – major chipmakers will demand extensive validation before adopting a non‑incumbent EDA stack.

Nevertheless, the 30 % wire‑length reduction aligns with the Tau Scaling Law presented by Huawei, which predicts that each additional vertical layer yields diminishing but still significant gains in speed and power efficiency. If the law holds, a modest 3‑layer LogicFolding implementation could already match the performance of a 5‑nm planar design, offering a cost‑effective pathway to compete with EUV‑based products.

Competitive response

Western vendors are unlikely to ignore the development. Both Synopsys and Cadence have announced AI‑assisted placement features that could be extended to vertical optimization, potentially blurring the line between chiplet stacking and intra‑die folding. However, their existing IP portfolios are heavily tied to EUV‑driven process nodes, which may limit immediate applicability to Huawei’s EUV‑free roadmap.

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Outlook

The Peking University prototype marks a significant technical milestone in the quest for truly three‑dimensional chip design. While commercial adoption will depend on rigorous validation and ecosystem build‑out, the reported 30 % wire‑length savings and associated performance/thermal benefits provide a concrete data point that could reshape how Chinese semiconductor firms approach advanced‑node scaling.

If the tool matures, it could become a cornerstone of China’s self‑reliant semiconductor strategy, offering a home‑grown alternative to the Western EDA monopoly and enabling Huawei—and potentially other Chinese fabless companies—to deliver high‑performance chips without EUV lithography.

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For more details on Huawei’s LogicFolding architecture, see the IEEE ISCAS 2026 presentation linked in the original announcement.