Senao SX906 Puts an Intel Xeon 6 SoC DPU on a PCIe Card

Senao showed the SX906 at Computex 2026, and the interesting part is not just that it is a high-end SmartNIC. The card is built around an Intel Xeon 6 SoC, specifically Granite Rapids-D class silicon, and exposes the device as a PCIe add-in card with dual 100GbE networking, onboard management, DDR5 memory channels, QuickAssist acceleration, and additional PCIe Gen5 connectivity.

That puts the SX906 in DPU territory. A conventional SmartNIC usually handles packet steering, offloads, crypto, virtual switching, telemetry, or storage protocol acceleration while leaving the host CPU in charge of the control plane. Senao’s card is closer to a server on a PCIe card. It has up to 38 Intel P-cores, four DDR5 memory channels, an ASPEED AST2600 BMC, Intel Platform Firmware Resilience support, and enough power draw to require platform-level planning rather than casual NIC slot installation.

The practical result is a device that can terminate and process high-throughput network traffic close to the wire while still running familiar x86 software stacks. That matters for service providers, telcos, storage systems, private cloud operators, and infrastructure teams that want DPU isolation without porting every workload to an Arm-based or custom accelerator environment. The SX906 is not trying to be the lowest-power programmable NIC in the rack. It is aiming at deployments where CPU locality, network bandwidth, PCIe attachment, and operational manageability are all part of the same design problem.

Technical announcement

The Senao SX906 was displayed as a dual-slot, full-height PCIe card using Intel Xeon 6 SoC processors in 24-core, 36-core, and 38-core configurations. The 24-core option is listed with 100Gbps total processor bandwidth, while the 36-core and 38-core options are listed for 200Gbps. The faceplate exposes two QSFP28 cages, which means the physical network interface is designed around 2 x 100GbE operation when paired with the higher-bandwidth SoC options.

The card also includes an Intel Ethernet Controller E830, positioning it in the same general class of infrastructure NIC technology used for high-rate packet processing, virtualization offloads, and data center Ethernet deployments. The distinction is that the Ethernet controller is not the whole product. It is attached to a Xeon 6 SoC complex that can run substantial control-plane and data-plane software directly on the card.

From the booth photos, the hardware still looked like an early sample, but the architecture is clear. Senao is combining a modern x86 SoC, high-speed Ethernet, PCIe Gen5 expansion, local memory, and out-of-band management into a card that can sit inside a host server while acting as a managed compute endpoint. That makes the SX906 relevant to designs where the infrastructure operator wants host isolation, network service chaining, packet inspection, storage offload, or tenant-facing acceleration without dedicating a separate 1U node to each function.

Specifications

The published card configuration lists three processor options: Intel Xeon 6523P-B with 24 cores at 2.5GHz, Intel Xeon 6553P-B with 36 cores at 2.6GHz, and Intel Xeon 6563P-B with 38 cores at 2.4GHz. All three are Intel Xeon 6 SoC parts, and all three include dual Intel QuickAssist Technology variants according to the article data. The 36-core and 38-core SKUs also add a media transcode accelerator, which is relevant for edge video processing, CDN ingest, real-time media gateways, and security analytics pipelines that need both packet movement and stream processing.

The networking side is straightforward on paper: 2 x 100G QSFP28, for up to 200GbE depending on the installed SoC. QSFP28 is common in 100GbE deployments and fits existing optics and cabling models better than a more exotic front-panel configuration would. The card’s host interface is listed as PCIe, and the board also exposes two PCIe Gen5 x8 MCIO connectors in addition to an x8 edge connector. In total, the design exposes 24 lanes of PCIe Gen5 connectivity.

That PCIe topology is one of the more interesting parts of the SX906. A DPU with only a host-facing edge connector can still offload networking, but it has limited options for building a small local fabric. With extra MCIO links, a card like this can attach to additional devices, expansion backplanes, storage, accelerators, or board-level interconnects depending on the system design. PCIe Gen5 x8 provides significant bandwidth per link, enough to make the SX906 a credible attachment point for more than basic management traffic.

Memory support is listed as four DDR5 channels. That gives the Xeon SoC local working memory instead of forcing every meaningful operation through the host. For packet processing, storage metadata handling, TLS/IPsec work, compression, telemetry buffering, or in-card control services, local memory bandwidth and capacity are major design variables. The exact DIMM or memory capacity configuration was not specified in the supplied material, but four channels indicate that this is built for real compute residency, not just firmware and descriptor queues.

Power is listed at 295W for the 24-core configuration and 355W for the 36-core and 38-core configurations. Power is delivered through the PCIe edge connector plus a 16-pin PCIe auxiliary power connector, commonly associated with 12VHPWR-style delivery. That number changes deployment assumptions. A 355W DPU card is in GPU power territory, so server qualification needs to account for slot spacing, airflow direction, cable routing, PSU headroom, thermal policy, and platform firmware behavior under load.

Cooling is dual-slot active cooling. The card is listed as FH10.5L+, with dimensions of 266mm x 98.4mm x 40.6mm and weight around 1kg. Those dimensions are manageable in GPU-capable servers, but they are not universal. Dense 1U platforms, front-I/O storage nodes, and systems with riser constraints will need mechanical validation. The SX906 is much more likely to fit naturally into 2U systems, GPU-style expansion nodes, and network appliance chassis designed for high-power add-in cards.

Management is another signal that this is a DPU rather than a simple NIC. The card includes an ASPEED AST2600 BMC, OpenBMC, an ASPEED AST1060 PFR controller, TPM 2.0 support for secure boot, and Intel Platform Firmware Resilience. The faceplate also includes management I/O, including RJ45 1GbE, USB 3.0 Type-C, console access, and Mini DisplayPort. That is the hardware profile of a managed compute node, even if it lives behind the host server’s PCIe slot.

Why the architecture matters

The SX906 sits at the intersection of three infrastructure trends. First, the network edge inside the server is getting more programmable. Second, cloud and enterprise operators want stronger isolation between tenant workloads and infrastructure services. Third, x86 compatibility still matters when teams already have observability agents, packet processing applications, encryption libraries, storage services, and operational tooling built around standard Linux environments.

A DPU built from Xeon P-cores changes the software porting question. Many DPU products use Arm cores or specialized packet engines, which can be efficient and well suited to the task, but they also require architecture validation and sometimes code changes. With a Xeon 6 SoC, more software can run with familiar compilation targets, debugging flows, performance counters, and deployment images. That does not remove the need for tuning, NUMA awareness, interrupt steering, queue placement, or memory locality work, but it reduces the architectural distance between the host and the infrastructure processor.

The cost is power. A 295W to 355W card has to earn its slot. The argument for this class of DPU is strongest when the alternative is burning more host CPU cores, adding separate appliance nodes, or giving tenants direct access to infrastructure-sensitive functions. If the workload only needs basic checksum offload, RSS, SR-IOV, or standard virtualization features, this is far more hardware than required. If the workload needs packet processing, encryption, storage services, and control-plane isolation at 100GbE or 200GbE rates, the power envelope starts to make more sense.

Benchmark and throughput considerations

The headline throughput figure is up to 200GbE, but infrastructure teams should read that as a platform capability rather than a workload guarantee. Sustained line-rate performance depends on packet size, traffic mix, flow count, memory access pattern, offload configuration, PCIe topology, software path, and whether the card is doing simple forwarding or heavier inspection and transformation.

At 200GbE, minimum-size packet processing is a different problem from bulk TCP throughput. A device can move large frames at high bandwidth while still struggling with small-packet rate if the software path is inefficient. For real qualification, operators should test at least three classes of workloads: large-frame throughput, mixed packet sizes that resemble production traffic, and worst-case small-packet behavior. They should also test with security and telemetry enabled, because encryption, flow accounting, filtering, and mirror traffic often expose bottlenecks that do not appear in clean synthetic forwarding tests.

QuickAssist is a major part of the story. Intel QAT can accelerate compression and cryptographic operations, which makes it relevant for TLS termination, IPsec, VPN gateways, storage compression, and service mesh infrastructure. The best-case design keeps traffic movement, crypto, and application policy close together on the card. The weak design sends data back and forth across PCIe too often, burning latency and host bandwidth. The SX906 gives architects the hardware pieces, but placement of the software pipeline will decide whether the card behaves like an accelerator or an expensive detour.

The 36-core and 38-core versions add media transcode acceleration, which broadens the deployment profile. A DPU with media support can sit near ingest, CDN, surveillance, conferencing, or AI preprocessing pipelines where video is arriving over high-speed Ethernet and needs to be transformed before storage or analysis. That is not a traditional SmartNIC workload, but it matches the broader DPU pattern: move specialized infrastructure work away from general host cores and closer to the I/O path.

Deployment considerations

The first deployment question is physical compatibility. The SX906 is dual-slot, full-height, 266mm long, and can consume up to 355W. That requires chassis airflow validation, not just a free PCIe slot. A server may accept a GPU-length card but still fail thermal requirements if the fan orientation, baffle layout, or riser position does not match the card’s cooling assumptions. In a production rack, inlet temperature, adjacent cards, cable density, and fan curves matter.

The second question is power delivery. A card using the PCIe edge connector plus a 16-pin auxiliary connector needs proper cabling and PSU support. Operators should verify connector rating, cable bend radius, retention, and service procedures. This is not a minor detail in dense systems. Poor auxiliary power routing can make card replacement slower, block airflow, or introduce avoidable reliability issues.

The third question is control-plane ownership. Because the SX906 has its own BMC and OpenBMC support, it may need to be managed as a device in its own right. That affects inventory, firmware update policy, secure boot enrollment, event logging, Redfish integration if available, and recovery procedures. Teams accustomed to treating NICs as host peripherals will need a different operational model. A Xeon DPU can have its own firmware lifecycle, host interface policy, and security boundary.

Security planning should include TPM 2.0, secure boot, PFR behavior, and the trust relationship between host and card. One of the reasons to deploy a DPU is to keep infrastructure services outside the tenant-controlled host environment. That benefit depends on configuring the boundary correctly. Firmware signing, attestation, management network isolation, and access control for the card’s BMC are part of the system design, not optional cleanup work after installation.

PCIe wiring also deserves attention. The card exposes an edge x8 link and two PCIe Gen5 x8 MCIO connectors. Depending on the server, those lanes can be used to attach the DPU to the host, to local expansion, or to a custom platform topology. Architects need to model bandwidth direction, peer-to-peer behavior, ACS/IOMMU policy, and failure handling. A DPU that sits between network and storage can reduce host involvement, but only if the PCIe fabric and software stack are built for that path.

Real-world implications

For cloud providers and private cloud operators, the SX906 points to a high-compute DPU model where virtual networking, storage services, firewalling, encryption, telemetry, and tenant isolation can live on a managed x86 endpoint. That can free host cores for customer workloads and give the infrastructure team a control plane that remains available even when the host OS is unhealthy. The trade-off is that each server becomes more complex, with another compute domain to provision, monitor, patch, and secure.

For network appliances, the card could reduce board design work. Instead of building a full custom server motherboard around a Xeon SoC and 200GbE networking, an appliance vendor could use a host platform plus the SX906 as a modular data-plane and service-plane element. That model is attractive when product SKUs need to scale across different chassis or when the same network processing card can be reused across firewall, load balancing, storage, and edge compute systems.

For storage systems, the combination of 200GbE, QAT, DDR5 memory channels, and PCIe Gen5 expansion suggests interesting NVMe-oF and compression paths. A DPU can terminate network storage protocols, perform encryption or compression, and steer data toward local PCIe devices while reducing host interrupts and CPU involvement. The hard part is preserving latency. Storage acceleration only works when queue handling, DMA paths, and memory placement are controlled carefully.

For edge deployments, the power envelope is both a strength and a warning. A Xeon 6 SoC card with media acceleration can process network and video workloads close to ingest points, but 355W is a serious requirement outside a conventional data center rack. Telecom edge sites, retail aggregation nodes, and industrial systems often have tighter power and cooling budgets. The SX906 is better aligned with high-density edge compute or central office infrastructure than small passive edge boxes.

The larger signal is that the DPU category is widening. Some products optimize for efficiency and fixed-function offloads. Others emphasize programmable packet pipelines. Senao’s SX906 takes the high-compute route: put a modern Xeon SoC on the card, give it high-speed networking, expose PCIe Gen5, add BMC-class management, and let operators run infrastructure services where the packets enter the server. That is not the right answer for every rack, but for teams already building around x86 software and 100GbE to 200GbE service rates, it is a serious option to evaluate.

Senao’s Computex card is interesting because it makes the boundary between server, NIC, and appliance less rigid. The SX906 is not just a faster adapter. It is a deployable infrastructure node in PCIe form, with the operational obligations that come with that design. For systems engineers, the key question is not whether the card is impressive on a spec sheet. The question is whether its compute, management, PCIe, and Ethernet resources can replace enough host work or external appliance capacity to justify the slot, the watts, and the added lifecycle management.