Silicon Motion SM2524XT pushes 14 GB/s to quad‑channel SSDs and trims KV‑cache latency

Announcement

Silicon Motion unveiled the SM2524XT, a 6 nm DRAM‑less SSD controller that promises 14 GB/s sequential reads and 2.5 M random IOPS on a four‑channel NAND interface. The company will showcase prototype drives at Computex, with volume products expected in 2025. By pairing a PCIe 5.0 x4 host link with NAND channels capable of 4,800 MT/s, the SM2524XT aims to bring high‑end performance into the mainstream market.

Technical specifications

Feature	Detail
Process node	TSMC 6 nm (N6 class)
CPU cores	Four Arm Cortex‑R series cores (exact model undisclosed)
DRAM	None – uses on‑chip SRAM and advanced ECC
NAND interface	Four channels, up to 4,800 MT/s each
Host interface	PCIe 5.0 x4 (32 GT/s)
Maximum sequential read	14 GB/s (≈ 112 Gb/s)
Maximum sequential write	Not disclosed, expected 9–10 GB/s based on similar designs
Random performance	Up to 2.5 M IOPS (4 KB reads)
Power envelope	5 W typical, 7 W peak (DRAM‑less advantage)
ECC	SMI NANDXtend LDPC, adaptive to TLC/QLC
AI‑optimizations	Separated Command Address (SCA), KV‑cache latency reduction
Compliance	NVM Express 2.0

How the 6 nm node matters

Moving from the previous 7 nm‑class SM2262XT to a true 6 nm class node reduces transistor leakage by roughly 15 % and improves clock speeds by 10‑12 %. The smaller pitch also allows Silicon Motion to integrate more on‑chip SRAM, which replaces the external DRAM cache while keeping latency under 80 ns for random reads – a figure comparable to low‑latency DRAM‑based solutions.

Quad‑channel vs. eight‑channel economics

Eight‑channel controllers such as Samsung’s PM9A1 or Western Digital’s WD_BLACK SN850X reach 14 GB/s by spreading data across eight NAND lanes, each limited to ~2,400 MT/s. The SM2524XT doubles the per‑lane speed to 4,800 MT/s, meaning the same aggregate bandwidth is achieved with half the channel count. Fewer channels translate to:

• Lower PCB real‑estate – a smaller footprint on the SSD PCB.
• Reduced BOM cost – fewer NAND dies and less complex routing.
• Improved power efficiency – fewer active lanes consume less power, an advantage for laptops and edge AI devices.

KV‑cache and AI inference focus

KV (key‑value) cache stores intermediate results from large language models (LLMs) or diffusion pipelines. In a typical on‑device inference scenario, a 12 GB LLM may generate 10‑20 KB of KV data per token, leading to thousands of random reads per second. The SM2524XT tackles this with two key techniques:

1. Separated Command Address (SCA) – command and address phases travel on separate physical lanes inside the NAND interface, allowing simultaneous processing. Benchmarks from Silicon Motion show a 25 % reduction in average KV‑cache latency compared with the SM2262XT.
2. Dynamic latency smoothing – the controller monitors queue depth and throttles background garbage‑collection traffic to keep latency spikes under 150 µs, a critical threshold for real‑time AI inference.

These features make the chip attractive not only for high‑performance PCs but also for edge AI boxes where DRAM is limited and power budgets are tight.

Market implications

1. Mainstream SSDs catch up to premium tier – Historically, only eight‑channel drives topped 14 GB/s. With the SM2524XT, manufacturers can ship 4‑channel SSDs that hit the same ceiling, narrowing the performance gap between consumer and enthusiast segments.
2. Cost pressure on DRAM‑based controllers – DRAM‑less designs cut BOM by 30‑40 %. As more OEMs adopt the SM2524XT, we may see price reductions of 10‑15 % for 2 TB drives that previously required a separate DRAM cache.
3. AI‑centric PC market acceleration – Laptop and desktop vendors targeting AI‑enhanced workloads (e.g., on‑device LLMs, AI‑assisted video editing) will likely favor SSDs built on this controller to avoid the latency bottlenecks that have limited current consumer drives.
4. Supply‑chain considerations – Silicon Motion relies on TSMC’s 6 nm capacity, which is already booked for high‑volume mobile SoCs. Any shift in TSMC allocation could affect SSD launch timelines, explaining the projected 2025 market entry.
5. Competitive response – Intel’s upcoming P‑Series SSDs and SK Hynix’s 3D‑V-NAND‑based controllers will need to either adopt higher‑speed NAND interfaces or add similar AI‑focused latency tricks to stay relevant in the mid‑range segment.

Outlook

The SM2524XT demonstrates that the industry can extract high‑end bandwidth from a quad‑channel architecture by leveraging faster NAND interfaces and aggressive on‑chip optimizations. If the promised latency improvements hold in real‑world AI workloads, we could see a new class of “AI‑ready” consumer SSDs that deliver desktop‑grade performance without the cost premium of DRAM‑backed designs. The next wave of products, likely announced after Computex, will reveal how quickly OEMs can integrate this controller into laptops, desktops, and edge AI appliances.