AMD published its first estimated benchmarks for the Zen 6-based EPYC 'Venice' processor, asserting a 3.3x rack-level performance advantage over Nvidia's Vera CPU within a fixed 100kW power envelope. The numbers are modeled rather than measured, and the framing matters as much as the figures.
AMD has released its first official performance estimates for EPYC 'Venice,' the server family that will be the first to ship with the company's Zen 6 architecture. The headline figure is aggressive: AMD claims the flagship 256-core part delivers 3.3 times the performance of Nvidia's Vera CPU in a rack-scale deployment constrained to a 100kW power budget. The full specifications of the chip remain undisclosed, but the company is clearly using these numbers to set the tone ahead of its Advancing AI event next month.
The constraints behind this claim change the interpretation entirely, so they deserve to come first. AMD is not comparing two sockets head to head. It is comparing what fits inside a single rack at a fixed power ceiling, then measuring aggregate throughput across that rack. A 256-core Venice part at a given TDP determines how many dual-socket nodes you can fit under 100kW, and that node count gets multiplied by per-node performance to reach the rack total. More cores per socket and better performance-per-watt compound at the rack level, which is where a 3.3x figure becomes plausible even if single-socket gains are more modest.
How the numbers were produced
This is a modeling exercise, not a tested rack. AMD's methodology paper, published alongside the results, lays out the chain of estimates. The company first calculated power draw from the processor TDP plus supporting components, used that to derive how many 2P nodes fit within 100kW, then multiplied that node count by single-node performance captured in a small set of benchmarks. No full 100kW deployment was actually built and measured. The per-node figures are real measurements; the rack-scale totals are extrapolations from them.
The benchmark suite is built around general-purpose data center work rather than anything AI-specific, despite AMD framing the story around agentic AI. The topline result comes from SPEC CPU 2017 integer throughput. The supporting tests include:
- Server-side Java via SPECjbb 2015
- WRK driving load against an NGINX web server
- redis-benchmark for in-memory workloads
- Memcached for memory caching
- TPROC-C on MySQL for database throughput
These are the workloads that actually populate enterprise racks, which is the point AMD wants to make. Core-heavy, throughput-bound jobs scale with socket density, and a 256-core Zen 6 part gives AMD a large lead in raw thread count to amortize across a power budget. Integer throughput on SPEC CPU 2017 rewards exactly that kind of width.
The competitive context
The timing is not incidental. These estimates landed after Phoronix published a set of Vera results that Nvidia itself had curated, and AMD's response reads as a direct counter. Both vendors are now publishing selective, favorable numbers for parts that aren't broadly available, which means neither set should be treated as a verdict. Vera is Nvidia's Arm-based data center CPU paired with its Rubin GPU generation, and the company has its own reasons to present it in the best light.
What AMD is really doing here is laying groundwork. The Advancing AI event next month is where Venice, Zen 6 across the broader product stack, and the enterprise roadmap are expected to get real detail: clock targets, full SKU breakdowns, process node confirmation, and the platform specifics that determine whether the rack-scale math holds in shipping hardware. Zen 6 is widely expected to move to a more advanced TSMC node, which would account for much of the performance-per-watt headroom these projections assume.
Until independent testing exists, the honest read is that AMD has shown a modeled advantage under conditions it selected, against a competitor part that is similarly pre-release. The 3.3x number tells you what AMD believes its core-count and efficiency strategy can deliver at the rack level. It does not yet tell you what a buyer will measure. The benchmarks AMD chose are credible and standard, the modeling approach is disclosed, and the rack-scale framing is a legitimate way to evaluate data center economics. All of that still sits on estimates rather than silicon in a lab. The figures worth waiting for are the ones from next month's event and, more importantly, the third-party reviews that follow Venice's actual launch.
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