Google Splits Its Next TPU Between TSMC and Samsung as Foundry Capacity Tightens

Google is in advanced talks with Samsung Electronics to manufacture part of its tenth-generation tensor processing unit, codenamed "Ice Fish," according to sources cited in recent reporting. The detail that matters for anyone tracking AI hardware is not that Samsung is involved, but exactly which part of the chip it would build, and why Google is splitting the work at all.

What's actually being claimed

The reported arrangement is specific. TSMC keeps the core compute die, fabricated on its 1.4-nanometer process. Samsung would produce the input/output die on its 2-nanometer Gate-All-Around (GAA) node. Separately, Google is said to be in talks with Intel about additional capacity, with a stated target of more than three million TPUs by 2028 and mass production of Ice Fish starting that same year.

If you parse the engineering, this is a disaggregated design. Modern accelerators are increasingly built as multiple dies packaged together rather than one monolithic piece of silicon. The compute die holds the matrix-multiply units that do the actual tensor math, and it benefits most from the densest, most expensive process available. The I/O die handles memory interfaces, chip-to-chip links, and other connectivity. That logic does not scale as well with each new node and gains less from being on the bleeding edge. Putting it on a slightly older 2nm process at a different foundry is a reasonable technical decision, not a compromise on performance.

What's actually new here

The interesting shift is the supplier split itself. For years, Google's TPUs (designed with Broadcom and fabricated at TSMC) were a single-foundry story. Multi-sourcing a flagship accelerator across two, possibly three, foundries is a meaningful change in procurement posture.

The reason is capacity, not price or politics. TSMC's leading-edge nodes are oversubscribed. Every large AI buyer, Nvidia, AMD, Apple, Google, Amazon, is competing for allocation on the same handful of fabrication lines, and lead times for advanced nodes have stretched to the point where allocation is a strategic constraint rather than a purchasing detail. When a single vendor cannot physically build enough wafers, diversification stops being a hedge and becomes the only way to hit volume targets.

This is where the three-million-unit figure is worth examining. Numbers like that are easy to announce and hard to verify, and 2028 is far enough out that targets routinely slip. Treat it as a statement of intent about scale rather than a delivery commitment. What it does tell you is that Google expects TPU demand, driven by both its own model training and external Google Cloud customers, to keep climbing steeply enough that no single foundry can serve it.

What this means for Samsung

For Samsung's foundry division, winning even the I/O die of a Google TPU would be a real credibility marker. Samsung has trailed TSMC on yield and on landing marquee external customers for its most advanced nodes. The reported Tesla deal from July 2025, a $16.5 billion agreement to produce AI chips on Samsung's 2nm process, and a planned second fab in Texas, point to a foundry trying to prove its GAA line can hold tight enough yields for demanding customers.

A word of caution on the framing, though. Building the I/O die is not the same as building the compute die. The hardest, highest-value silicon stays at TSMC. Samsung getting the connectivity die is genuine business and a vote of confidence, but it is not evidence that Samsung has closed the gap on leading-edge logic. The split arguably shows the opposite: Google trusts Samsung with the part that tolerates an older node, and keeps the part that needs the best process where it has always been.

The broader pattern

Step back and the same dynamic shows up across the industry. The bottleneck in AI hardware has moved. A few years ago the constraint was design talent and software. Then it was high-bandwidth memory and CoWoS-style advanced packaging. Now it is increasingly raw wafer capacity at the front of the leading-edge nodes, plus the packaging to assemble these multi-die parts.

Google's response, spreading a single product across TSMC, Samsung, and potentially Intel, is what a buyer does when supply, not demand, is the limiting factor. It also quietly validates the chiplet approach. Disaggregating a design into separate dies is what makes multi-foundry sourcing practical in the first place, because you can route each die to whichever fab can best produce it. Expect more accelerators to be built this way, less because it is elegant and more because it gives procurement teams options when any one supplier runs short.

None of this changes the near-term reality that Nvidia GPUs still dominate AI compute and that TPUs remain primarily a Google Cloud and internal play. But the manufacturing strategy behind Ice Fish is a useful signal. The companies building the most accelerators are now planning around the assumption that the foundries cannot keep up, and they are restructuring both their chips and their supplier relationships accordingly. For more on Google's accelerator family, see the Cloud TPU documentation, and Samsung's foundry roadmap is outlined on its foundry site.