IBM and Lam Research Partner to Push Logic Scaling Beyond 1nm with High NA EUV Dry Resist

IBM and Lam Research have announced a five-year collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using High NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's facilities at the NY Creates Albany NanoTech Complex in Albany, New York.

(Image credit: IBM Research)

The two companies have worked together for more than a decade, contributing to 7nm process development, nanosheet transistor architecture, and early EUV process integration, with IBM unveiling what it described as the world's first 2nm node chip in 2021 as part of that ongoing partnership.

Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.

Conventional EUV lithography relies on chemically amplified resists, wet-process materials that struggle with the tighter tolerances demanded by high-NA EUV scanners. Meanwhile, Lam's Aether technology is a dry resist, deposited via vapor-phase precursors rather than spin-coating, and developed using plasma-based dry processes.

Aether's metal-organic compounds absorb three to five times more EUV light than traditional carbon-based resist materials, which reduces the exposure dose needed per wafer pass and helps maintain single-print patterning at advanced nodes without resorting to more expensive multi-patterning. In January, Lam announced Aether had been selected by a leading memory manufacturer as the production tool of record for its most advanced DRAM processes, though it did not name the manufacturer.

According to the joint announcement, the collaboration seeks to enable High NA EUV patterns to be reliably transferred into real device layers at high yield, and to accelerate industry adoption of High NA EUV for next-generation interconnect and device patterning. That yield-at-transfer problem is where Lam's Aether dry resist technology has an edge over conventional wet processes, because fewer steps between exposure and etch mean less opportunity for pattern degradation at tighter geometries.

Meanwhile, nanosheet transistors stack multiple thin sheets of silicon to increase drive current without widening the device footprint. The press release confirms the teams will build and validate full process flows for both nanosheet and nanostack devices, alongside backside power delivery, which routes power through the back of the wafer to free up front-side interconnect layers for signal routing.

"Together, these capabilities are aimed at allowing High‑NA EUV patterns to be reliably transferred into real device layers with high yield and enabling continued scaling, improved performance, and viable paths to production for future logic devices," says the press release.

The collaboration represents a significant investment in pushing semiconductor manufacturing beyond the 1nm threshold, a point where conventional scaling approaches face fundamental physical limitations. High NA EUV lithography, which uses a numerical aperture of 0.55 compared to the 0.33 used in current EUV systems, enables finer resolution but demands new materials and processes to achieve the required precision.

Aether's dry resist technology addresses several critical challenges in high-NA EUV processing. By eliminating the need for wet development steps, it reduces defectivity and pattern collapse risks that become severe at sub-1nm dimensions. The vapor-phase deposition process also enables more uniform coating on high-aspect-ratio features and complex 3D structures, which are increasingly common in advanced logic devices.

The nanostack architecture represents another key innovation being pursued through this partnership. By vertically stacking multiple nanosheet transistors, chip designers can achieve higher transistor density without reducing individual sheet thickness to impractical levels. This approach maintains performance characteristics while potentially reducing manufacturing complexity compared to extreme fin or gate-all-around structures.

Backside power delivery, the third major technology in development, addresses the interconnect bottleneck that threatens to limit scaling regardless of transistor size. By routing power through the wafer's backside, this technique frees up multiple interconnect layers for signal routing, potentially improving performance and reducing power consumption in advanced logic chips.

The Albany NanoTech Complex, where this work will be conducted, provides the specialized equipment and cleanroom facilities necessary for developing these advanced processes. The facility's track record includes multiple process technology breakthroughs and serves as a proving ground for next-generation semiconductor manufacturing techniques before they reach commercial production.

This collaboration comes at a critical time for the semiconductor industry, as traditional scaling approaches approach their physical limits. The combination of High NA EUV, advanced dry resists, novel device architectures, and innovative interconnect schemes represents a comprehensive approach to extending Moore's Law beyond what was previously thought possible.

The five-year timeline suggests these technologies are still in early development stages, with significant work needed to validate them for high-volume manufacturing. However, the involvement of both a major chip designer (IBM) and a leading equipment manufacturer (Lam Research) indicates strong industry commitment to overcoming the technical challenges of sub-1nm scaling.

If successful, this partnership could help maintain the semiconductor industry's historical pace of performance improvement, enabling continued advances in computing power for applications ranging from artificial intelligence to scientific computing. The technologies developed through this collaboration may also find applications in other areas of semiconductor manufacturing, potentially accelerating innovation across the industry.