Intel Xeon 7 ‘Diamond Rapids’ Set for 2027 Launch on Refined 18A‑P Node

Announcement

Intel confirmed that its next‑generation Xeon 7 line, codenamed Diamond Rapids, will ship in 2027 on the refined 18A‑P process node. The company revealed the key headline specs during a Q&A at Computex and said a deeper technical briefing is planned for the Hot Chips conference this summer.

Image credit: Intel

Technical specifications

Process node and performance uplift

• 18A‑P is a tuned iteration of Intel’s 18 Å (nanometer) FinFET platform. Intel claims a 9 % performance gain at the same power envelope as the baseline 18A, or an 18 % power reduction for equivalent performance. The node also includes tighter voltage control and higher defect‑density yields, which Intel hopes will make the process attractive to external foundry customers.
• The node will support PCIe 6.0 with a theoretical 64 GT/s per lane, matching the bandwidth of competing AMD and Nvidia offerings.

Core count and architecture

• Diamond Rapids will debut as an E‑core‑only design, continuing the trend set by the Xeon 6+ family. Intel cited a 50 % increase over the top‑end Granite Rapids‑AP part (128 cores), which translates to 192 cores for the initial Xeon 7 SKU.
• Rumors of a 256‑core or even 512‑core variant have been dismissed for now; Intel has not announced any such densities.
• The cores are expected to be based on the Panther Cove microarchitecture, an evolution of the P‑core family used in recent client silicon. Intel’s January earnings call hinted at a return of Hyper‑Threading later in the roadmap, but no confirmation has been given for the Xeon 7 launch.

Memory subsystem

• Diamond Rapids will ship exclusively with a 16‑channel DDR5 memory interface, abandoning the 8‑channel option explored for earlier Xeon 7 prototypes.
• Granite Rapids‑AP (12‑channel) delivered 614 GB/s peak bandwidth, while the 8‑channel Granite Rapids‑SP topped at 409 GB/s. Doubling the channel count pushes the theoretical ceiling to at least 1.2 TB/s (16 × 75 GB/s per channel) and 818 GB/s if the 12‑channel baseline is used for comparison.
• Support for second‑generation MRDIMM modules could raise the ceiling to 1.6 TB/s per socket, a figure that would outpace AMD’s Venice launch specifications.

I/O and accelerators

• In addition to PCIe 6.0, the Xeon 7 platform will retain CXL 2.0 compatibility, enabling high‑speed memory expansion and accelerator attachment.
• Intel has not yet disclosed the number of integrated AI matrix engines or FPGA fabric options, but the 18A‑P node’s higher transistor density should allow more heterogeneous blocks per die.

Market implications

Competitive timing

• AMD plans to launch its Zen 6‑based EPYC Venice CPUs in 2026, with up to 256 cores, 1.6 TB/s memory bandwidth per socket, and a claimed 70 % generational performance uplift. The earlier market entry gives AMD a head‑start in securing high‑density server contracts.
• Intel’s 2027 Xeon 7 timeline compresses the gap but still leaves a full year for AMD to capture early‑adopter revenue, especially in hyperscale cloud environments that prioritize rapid refresh cycles.

Supply‑chain considerations

• The 18A‑P node is a refined version of 18A, which Intel demonstrated at its recent Foundry Day. The refinement focuses on yield improvements and voltage stability, both critical for meeting the massive wafer‑count demands of data‑center silicon.
• Intel’s emphasis on external foundry customers suggests that 18A‑P capacity may be shared with other fab partners, potentially smoothing out the historically tight supply of Xeon silicon.
• However, the shift to a 16‑channel memory design eliminates the lower‑cost 8‑channel variant, which could affect price‑sensitive segments that previously leveraged the cheaper memory stack.

Performance outlook

• Assuming the 9 % IPC gain and 18 % power reduction hold across the full core count, a 192‑core Diamond Rapids part could deliver ~2.1× the compute throughput of the 128‑core Granite Rapids‑AP at the same TDP.
• The combination of PCIe 6.0 and CXL 2.0 positions the platform for next‑gen accelerator ecosystems, such as AI inference cards and high‑speed storage arrays, which are increasingly bandwidth‑bound.
• If Intel re‑introduces Hyper‑Threading on the Panther Cove cores for later Xeon 7 SKUs, effective thread counts could rise to 384 logical threads, narrowing the gap with AMD’s simultaneous‑multithreading approach.

Outlook for the roadmap

• Intel has already hinted at Coral Rapids for 2028, which is expected to bring SMT (Simultaneous Multithreading) back to the Xeon line and further improve per‑core efficiency.
• The timing suggests a two‑year cadence between major Xeon releases (Xeon 6+ in 2025, Xeon 7 in 2027, Coral Rapids in 2028), aligning with the industry’s move toward heterogeneous compute rather than pure core count scaling.

---

The Xeon 7 ‘Diamond Rapids’ announcement underscores Intel’s strategy of incremental process refinement and architectural consolidation to regain momentum in the high‑end server market. While AMD retains a temporal advantage with Venice, the higher memory bandwidth, PCIe 6.0 support, and potential power efficiency gains of Diamond Rapids could make it a compelling option for customers prioritizing total‑system throughput and energy cost.

---

Sources

• Intel press release on Xeon 7 launch (link pending)
• Intel 18A‑P process details
• AMD EPYC Venice roadmap (AMD newsroom)
• Hot Chips conference schedule (https://hotchips.org)