Apple's new M5 Pro and M5 Max chips introduce a third core type, creating confusion with the renaming of existing cores from 'performance' to 'super cores.' Here's what developers and users need to know about the new architecture.
Apple's latest M5 Pro and M5 Max chips represent a significant evolution in Apple Silicon architecture, introducing a third type of CPU core that sits between the traditional efficiency and performance cores. However, this advancement comes with a naming complication that has left many developers and users scratching their heads.

Prior to yesterday's launch, Apple Silicon chips featured two core types: efficiency cores for everyday tasks and performance cores for demanding workloads. The new M5 chips maintain this foundation but add a middle ground with a new core type, while simultaneously renaming the existing performance cores to "super cores."
The naming convention now looks like this:
| Old name | New name |
|---|---|
| Efficiency | Efficiency |
| Performance | Super |
| Performance (new) | Performance |
This creates a somewhat confusing situation where what was previously called a "performance core" is now a "super core," and the new middle-tier core is called a "performance core."
A clearer way to think about the three core types would be:
- Efficiency cores: Handle lightweight, everyday tasks to maximize battery life
- Performance cores: The new middle tier, balancing power and efficiency
- Super cores: The high-performance cores for demanding workloads
John Gruber spoke with Apple to clarify these changes and provided a breakdown of core configurations across the new MacBook Pro models:
| Core Type | M5 | M5 Pro (15-core) | M5 Pro (18-core) | M5 Max |
|---|---|---|---|---|
| Efficiency | 6 | — | — | — |
| Performance | — | 10 | 12 | 12 |
| Super | 4 | 5 | 6 | 6 |
This table reveals an interesting design choice: the higher-end M5 Pro and M5 Max chips don't include any efficiency cores at all. Instead, they rely on the new performance cores to handle the power efficiency requirements while delivering enhanced performance.
The original Apple Silicon architecture was revolutionary because it offered both exceptional performance and unprecedented power efficiency compared to Intel chips. This was achieved through the intelligent distribution of workloads between efficiency and performance cores. With the M5 generation, Apple is refining this approach by adding granularity to the performance spectrum.
For developers, this three-tier core architecture means more sophisticated workload management. The operating system can now make finer-grained decisions about which type of core to use for specific tasks, potentially leading to better performance and battery life. However, it also means that performance profiling and optimization may become more complex as applications need to account for three distinct core types rather than two.
The base M5 chip remains largely unchanged from its predecessors, maintaining six efficiency cores and four super cores (previously called performance cores). This suggests Apple is taking an incremental approach with its entry-level chip while pushing the boundaries with its higher-end offerings.
For users, the practical impact will likely be improved responsiveness for everyday tasks (handled by the new performance cores) while still maintaining excellent battery life and the ability to tackle demanding workloads when needed (handled by the super cores).
This architectural evolution continues Apple's trend of vertical integration and custom silicon design, allowing for optimizations that wouldn't be possible with off-the-shelf components. As Apple Silicon matures, we can expect to see further refinements to this core architecture, potentially including additional core types or more sophisticated power management features.
The naming confusion aside, the addition of a third core type represents Apple's ongoing commitment to balancing performance and efficiency in its devices. Whether this three-tier approach becomes the new standard for future Apple Silicon chips remains to be seen, but it certainly provides more flexibility in how tasks are distributed across the chip's resources.

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