AMD unveils groundbreaking Venice server CPUs and MI400 accelerators at CES 2026, featuring radical packaging innovations, massive core counts, and new V-Cache designs that redefine datacenter computing.
At CES 2026, AMD pulled back the curtain on two revolutionary system-on-chips destined to reshape datacenter computing: the Venice server CPU and MI400 accelerator series. These designs showcase unprecedented packaging innovations and architectural leaps that push beyond AMD's existing EPYC and Instinct product lines.
Venice: Dual-IO Die Revolution
Venice marks a radical departure from traditional EPYC designs. Unlike previous single-IO-die configurations, Venice features two IO dies connected via advanced packaging resembling AMD's Strix Halo technology. Each package contains eight Compute Chiplet Dies (CCDs) housing 32 Zen 6 cores apiece – enabling a staggering 256 cores per socket.
Our analysis reveals:
- CCDs fabricated on 2nm process at ~165mm² each
- Estimated Zen 6 core size of ~5mm² (comparable to Zen 5 on N3)
- Dual IO dies totaling >700mm² silicon (75% larger than Genoa)
- Eight mystery companion dies (likely capacitor arrays for power delivery)
The dual-IO architecture suggests doubled memory channels and unprecedented bandwidth – a necessary evolution for feeding 256 hungry cores.
MI400: 12-Die Powerhouse
The MI400 accelerator is an engineering marvel featuring 12 HBM4 stacks and 12 compute/IO dies in a single package. The complex arrangement includes:
- Two base dies (~747mm² each)
- Two dedicated IO dies (~220mm² each)
- Eight compute dies (estimated 140-160mm²)
- Hybrid 2nm/3nm fabrication
The "sandwich" design improves upon MI350's architecture with additional dies handling off-package connectivity (PCIe 6.0, UALink). This modular approach allows mixing specialized dies – potentially enabling custom configurations for AI workloads.
Expanding the Family
Beyond Venice and MI455X, AMD announced:
- MI440X – Slot-compatible upgrade for existing MI300/350 systems
- Venice-X – Game-changing V-Cache variant
The Venice-X revelation is particularly significant. If AMD applies its 3D V-Cache technology to the 32-core CCDs, each could hold 384MB of L3 cache – creating a monstrous 3GB total L3 cache per socket. This would represent the first V-Cache implementation on high-core-count server CCDs.
The Road Ahead
Both Venice and MI400 series are slated for late 2026 launches. When combined in AMD's Helios AI Rack, these architectures promise unprecedented compute density. The packaging innovations shown here – particularly Venice's dual-IO design and MI400's multi-die integration – demonstrate AMD's commitment to pushing boundaries in the post-Moore's-Law era.
Subscribe for architectural deep dives when these chips launch later this year.
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